An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments enable efficient and effective random generation of test input information. In one embodiment a method includes accessing a plurality of data values to write to a DUT, generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values, wherein assignments of a particular address to different respective ones of the data values are randomly repeatable; and directing writing of the data values to the DUT in accordance with the plurality of addresses that are randomly generated and randomly repeated. The generating a plurality of addresses randomly can include normalization. Generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values can include performing a confirmation check. The confirmation check can include checking if the addresses within proper parameters.

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.

In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

A first pre-sense amplifier connected to reference cells that hold data of logical value 1 via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.