A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.

A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.

The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

Aspects of the present disclosure are directed to generating endurance measures for a memory sub-system and using endurance measures to classify memory sub-systems, to predict memory system remaining life, and to create memory systems with consistently performing sub-systems. An endurance measure can be generated by computing multiple metric points. Each metric point can be based on a margin between a point, in cumulative distribution function (CDF)-based data at an acceptable memory unit failure rate, and an error amount threshold condition. Once a there are sufficient metric points related to the memory device, the metric points can be fit to a function. The endurance measure is then obtained by extrapolating the function to a point at which the function reaches a threshold.

An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.

Disclosed is a storage test apparatus having a storage protocol matching device including an integrated protocol software unit and an integrated protocol hardware unit, in which, when an insertion of a storage is detected, a protocol configuration that matches a protocol of the storage is automatically set through a protocol switching, thereby enhancing the test efficiency.

A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.

A testing system is provided. The testing system includes: test equipment and a testing-control apparatus. The test equipment is configured to perform tests on a device under test. The testing-control apparatus is configured to execute a test program to control the test equipment to perform a plurality of first test items in the test program on the device under test. The testing-control apparatus retrieves a test result of each of the first test items from the test equipment, and executes a test-program neural network to analyze the test result of each of the first test items to generate the test program for a next test iteration.

Aspects of the present disclosure are directed to generating endurance measures for a memory sub-system and using endurance measures to classify memory sub-systems, to predict memory system remaining life, and to create memory systems with consistently performing sub-systems. An endurance measure can be generated by computing multiple metric points. Each metric point can be based on a margin between a point, in cumulative distribution function (CDF)-based data at an acceptable memory unit failure rate, and an error amount threshold condition. Once a there are sufficient metric points related to the memory device, the metric points can be fit to a function. The endurance measure is then obtained by extrapolating the function to a point at which the function reaches a threshold.