Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.

An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.

The present disclosure provides a test method, system, medium and device for a dual in-line memory module, the test method includes: obtaining a position of the dual in-line memory module on a server; modifying a protection mechanism after detecting a defective dual in-line memory module; testing each dual in-line memory module; storing the test result in a system event log of the baseboard management control module. The test method, system, medium and device for a dual in-line memory module of the present disclosure is to prevent the server from being shut down during the test of the dual in-line memory module, and timely discover the defective dual in-line memory module.

Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

A method for monitoring communications between a device under test (DUT) and an automated test equipment (ATE) is disclosed. The method comprises programming an interface core and a protocol analyzer module onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test a DUT, wherein the interface core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method also comprises monitoring data and command traffic associated with the protocol in the interface core using the protocol analyzer module and storing results associated with the monitoring in a memory comprised within the protocol analyzer module. The method finally comprises transmitting the results upon request to an application program associated with the protocol analyzer module executing on the system controller.

A first pre-sense amplifier connected to reference cells that hold data of logical value 1 via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

A semiconductor integrated circuit according to an embodiment includes: a first circuit, an analog-to-digital converter, an external input terminal, a selector, and a second circuit. The first circuit is configured to generate a first voltage corresponding to a temperature. The analog-to-digital converter is configured to convert the first voltage into a first digital value. The external input terminal is a terminal to which a second digital value is input from outside. The selector is configured to select either the first digital value or the second digital value. The second circuit is configured to generate a second voltage based on a third digital value being a digital value selected by the selector.