Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

A method of repairing a storage device including a non-volatile memory includes powering on the storage device, performing a booting sequence, determining whether an error has occurred during the booting sequence or during a normal mode, writing a failure signature to a predetermined signature address in the non-volatile memory upon determining that the error has occurred, reporting a failure to a host upon writing the failure signature, entering into a repair mode upon reporting the failure, and operating in the normal mode upon determining that the error has not occurred.

The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.

Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.

Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

A method for operating a memory includes: activating a first row, and sensing and amplifying, by a first bit line sense amplifier array, data of memory cells of the first row; transferring data of first columns of the first row from the first bit line sense amplifier array to global input/output lines through first input/output sense amplifiers; storing data of the global input/output lines in the first columns of a dummy bit line sense amplifier array through dummy write drivers; transferring data of second columns of the first row from the first bit line sense amplifier array to the global input/output lines through the first input/output sense amplifiers; and storing the data of the global input/output lines in the second columns of the dummy bit line sense amplifier array through the dummy write drivers.

A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

A storage device includes a plurality of nonvolatile memory devices, a storage controller circuit and a leakage detection circuit. The storage controller circuit controls a plurality of nonvolatile memory devices, the storage controller circuit includes a plurality of connection terminals, each of the plurality of connection terminals is commonly connected to a corresponding set of pins, from among the pluralities of pins included in the plurality of nonvolatile memory devices, via a corresponding connection node, from among a plurality of connection nodes. The pins included in each set of pins have a same attribute. The leakage detection circuit is configured to determine whether leakage occurs at each set of pins based on the merged signal generated by the connection node connected to each set of pins, and configured to provide the storage controller circuit with a detection signal indicating a result of the determination.