Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.

A system and method of storing and reading digital data, including providing a nanopore polymer memory (NPM) device having at least one memory cell comprising at least two addition chambers each arranged to add a unique chemical construct (or codes) to a polymer (or DNA) string when the polymer enters the respective addition chamber, the data comprising a series of codes; successively steering the polymer from deblock chambers through the nanopore into the addition chambers to add codes to the polymer to create the digital data pattern on the polymer; and accurately controlling the bit rate of the polymer using a servo controller. The device may have loading chamber(s) to load (or remove) the polymer into/from the deblock chambers through at least one “micro-hole”. The cell may be part of a memory system that stores and retrieves “raw” data and allows for remote retrieval and conversion. The cell may store multi-bit data having a plurality of states for the codes.

A storage system determines source addresses, and destination addresses in a storage system, for network traffic. The storage system determines a hash algorithm, from a plurality of hash algorithms. The hash algorithm is to be used across the source addresses for load-balancing the network traffic to the destination addresses. The storage system determines that the hash algorithm more closely meets one or more load-balancing criteria than at least one other hash algorithm, of the plurality of hash algorithms. The storage system distributes the network traffic from the source addresses to the destination addresses in the storage system, with load-balancing according to the determined hash algorithm.

A system and method of storing and reading digital data, including providing a nanopore polymer memory (NPM) device having at least one memory cell comprising at least two addition chambers each arranged to add a unique chemical construct (or codes) to a polymer (or DNA) string when the polymer enters the respective addition chamber, the data comprising a series of codes; successively steering the polymer from deblock chambers through the nanopore into the addition chambers to add codes to the polymer to create the digital data pattern on the polymer; and accurately controlling the bit rate of the polymer using a servo controller. The device may have loading chamber(s) to load (or remove) the polymer into/from the deblock chambers through at least one “micro-hole”. The cell may be part of a memory system that stores and retrieves “raw” data and allows for remote retrieval and conversion. The cell may store multi-bit data having a plurality of states for the codes.

A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.

A method and a controller for recovering data in event of a program failure and a storage system using the method and the controller are disclosed. The controller includes main units of a parity generator, a volatile memory module and a processor. With a parity in the volatile memory module and successfully programmed sub-data, a program failed write data can be recovered and correctly programmed. The method of the present invention has advantages of saving use of storage resources and extending lifetime of the storage system than other methods for recovering data in event of a program failure.

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.

A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.