There are provided an electronic device, and more particularly, to a controller of a semiconductor memory device with an increased operation speed and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes obtaining a recovery address in which recovered data stored in a page buffer of the semiconductor memory device in which the program fail is generated is to be stored, transmitting a recovery command requesting the semiconductor memory device to transmit the recovered data to the semiconductor memory device, and storing the recovered data in the recovery address. The obtaining of the recovery address, the transmitting of the recovery command, and the storing of the recovered data in the recovery address are simultaneously performed while a post-processing operation is performed on the program fail.

Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.

An electronic device including a semiconductor memory unit that includes: a first access line coupled to a first memory cell; a second access line coupled to a second memory cell for replacing the first memory cell when the first memory cell is a failure memory cell; a first driving block coupled to one of the first access line and the second access line, and suitable for driving said one of the first access line and the second access line with a first voltage when the first memory cell is accessed; and a first repair coupling block suitable for selectively coupling the first access line and the second access line based on whether the first memory cell is a failure memory cell or not when the first memory cell is accessed.

Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

A semiconductor apparatus including a semiconductor chip is disclosed. The semiconductor chip includes a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses are randomly formed related to a part or a whole of the modular area of the modular region. The test circuit outputs a random number generated from physical properties intrinsic to the semiconductor chip according to a specification code received from a physical-chip-identification measuring device.

An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.

According to one embodiment, a memory includes a magnetoresistive element, a reference cell, a sense amplifier comparing a first current flowing in the magnetoresistive element with a second current flowing in the reference cell, a first transistor having a first control terminal controlling a value of the first current, a second transistor having a second control terminal controlling a value of the second current, and a controller applying a first potential to the first control terminal and a second potential to the second control terminal in a first operation, and applying the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation.

A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.