A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, tire package test, tire module test or the mounting test is failed.

There are provided a memory system and an operating method of the memory system. The memory system includes: a memory device including a plurality of semiconductor memories; and a controller for controlling the memory device to perform a bad block detection operation on free blocks among a plurality of memory blocks included in a selected semiconductor memory among the plurality of semiconductor memories. The controller selects, as a target memory block, memory blocks adjacent to a bad bock detected based on a result of the bad block detection operation, and controls the memory device to perform the bad block detection operation on the target memory block.

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.

A controller includes an interface and storage circuitry. The interface communicates with one or more memory devices, each of the memory devices includes multiple memory cells organized in memory blocks. The storage circuitry is configured to perform multiple storage operations to the memory cells in the one or more memory devices, and mark memory blocks in which one or more storage operations have failed as bad blocks. The controller is further configured to identify a pattern of multiple bad blocks occurring over a sequence of multiple consecutive storage operations, the pattern is indicative of a system-level malfunction in a memory system including the controller, and in response to identifying the pattern, to perform a corrective action to the memory system.

Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.