The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors. In another embodiment, the sensing amplifier utilizes sloped timing for the reference signal to increase the margin by which a “0” or “1” are detected from the current drawn by the selected cell compared to the reference cell. In an another embodiment, a sensing amplifier is used without any voltage offset.

Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.

Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.

The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.

The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors. In another embodiment, the sensing amplifier utilizes sloped timing for the reference signal to increase the margin by which a 0 or 1 are detected from the current drawn by the selected cell compared to the reference cell. In an another embodiment, a sensing amplifier is used without any voltage offset.

Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.