The application relates to a data reading circuit of an embedded flash memory cell. The data reading circuit a switch circuit, a current clamp circuit, a current mirror circuit, a reference current source, a precharge circuit and a comparison circuit; the switch circuit includes a transmission gate, one end of the transmission gate is connected with a drain of the embedded flash memory cell, and the other end of the transmission gate is connected with a detection end of the current clamp circuit; a response end of the current clamp circuit is connected with a data node; the current mirror circuit is connected with the reference current source and the data node; an output end of the precharge circuit is connected with the data node; one input end of the comparison circuit is connected with the data node, and the other input end is connected with reference voltage.

Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line.

In accordance with an embodiment, a circuit includes: a trimmable reference current generator having a temperature dependent current output node, the trimmable reference current generator including: a proportional to absolute temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including a first output coupled to the temperature dependent current output node; and a reference interface circuit having an input coupled to the temperature dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

A one-time programmable (OTP) memory device includes an OTP memory cell array comprising a plurality of dummy cells and a plurality of main cell groups of main cells and an access circuit configured to write data to at least two of the cells simultaneously. The arrangement of the dummy cells and the main cell groups may allow for the reliable writing of multi-bit data to the memory array. Each of the main cell groups may include a plurality of main cells which are connected to word lines, respectively, and to bit lines, respectively. Each of the main cells may be writable and each of the dummy cells may be unwritable. Each of the main cells may include a contact layer, and the dummy cells might not include the contact layer. A supply voltage may be applied to the OTP memory cell array through the contact layer.

Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit.

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

A sensing circuit for a non-volatile memory device is provided. The sensing circuit includes a bias generating circuit and a first sense amplifier. The bias generating circuit includes a driving circuit biased by a reference current and an operational amplifier. The operation amplifier receives a reference voltage at a non-inverting input terminal, and generates an output voltage at an inverting input terminal via a negative feedback path including the driving circuit. The first sense amplifier includes a first replica circuit and a first current sensing circuit. The first replica circuit replicates the output voltage to a first bit line coupled to a first memory cell. The first current sensing circuit senses a first current difference between a scaled version of the reference current and a first cell current of the first memory cell to determine a first memory state of the first memory cell.

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

A circuit for reading a programmed resistive state of resistive elements of a resistive memory, wherein each resistive element may be programmed to be in a first or a second resistive state, wherein the circuit includes a current integrator suitable for integrating a difference in current between a reading current flowing through a first of the resistive elements and a reference current.