A comparison device includes an MSB voltage generation circuit that includes a control signal terminal to generate an MSB voltage; a comparison circuit including a first input terminal receiving a first input signal and a second input terminal receiving a second input signal modified by the MSB voltage outputted from the MSB voltage generation circuit to move to a desired voltage range by comparing the first input signal with the modified second input signal to output an MSB comparison result signal, the comparison circuit, after the first input signal has reached the desired voltage range, comparing the first input signal with a residue voltage and outputting an LSB comparison result signal; and a control circuit receiving the comparison signal and operable to detect a crossing of the first input signal and the second input signal according to the MSB comparison result signal and to output the MSB voltage control signal.

Disclosed are methods, systems and devices for operation of memory device. In one aspect, a bitcell may represent a binary value, symbol, parameter or condition based on complementary impedance states of first and second memory elements. In one aspect, a first bitline and a second bitline may be coupled to terminals of the first and second memory elements. A circuit may detect the complementary impedance states responsive to a difference in a rates of charging of the first and second bitlines.

A circuit for reading a programmed resistive state of resistive elements of a resistive memory, wherein each resistive element may be programmed to be in a first or a second resistive state, wherein the circuit includes a current integrator suitable for integrating a difference in current between a reading current flowing through a first of the resistive elements and a reference current.

A comparison device includes an MSB voltage generation circuit that includes a control signal terminal to generate an MSB voltage; a comparison circuit including a first input terminal receiving a first input signal and a second input terminal receiving a second input signal modified by the MSB voltage outputted from the MSB voltage generation circuit to move to a desired voltage range by comparing the first input signal with the modified second input signal to output an MSB comparison result signal, the comparison circuit, after the first input signal has reached the desired voltage range, comparing the first input signal with a residue voltage and outputting an LSB comparison result signal; and a control circuit receiving the comparison signal and operable to detect a crossing of the first input signal and the second input signal according to the MSB comparison result signal and to output the MSB voltage control signal.

A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time to digital convertor converts a time associated with the output voltage to a digital value.

Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.