A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, a DBI port being configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.

Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.

The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.

A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.