A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row address in response to the memory controller's servicing of its request stream being stalled because of a timing constraint that prevents a change in row address. The memory controller also includes a cache to cache the prefetched data. The memory controller also includes circuitry to compare addresses of read requests in the memory controller's request stream against respective addresses of the prefetched data in the cache and to service those of the requests in the memory controller's request stream having a matching address with corresponding ones of the prefetched data in the cache.

Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.

Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.

Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.

An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

Embodiments provide a write operation circuit, a semiconductor memory, and write operation method. The write operation circuit includes: a data determination module that determines whether to flip an input data of the semiconductor memory depending on the number of high data bits in the input data so as to generate a flip flag data and a first intermediate data; a data buffer module that determines whether to flip a global bus according to a second intermediate data, where the second intermediate data is an inverted data of the first intermediate data; a data receiving module that decodes the global bus data according to the flip flag data and writes the decoded data into a memory bank of the semiconductor, where the decoding including determining whether to flip the global bus data; and a precharge module that sets the initial state of the global bus to low.

Provided is a data bus driving circuit including: a data processing unit that processes input data and outputs processed data; a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.