A semiconductor storing apparatus capable of performing continuous readout between multiple chips in high speed is provided. A NAND-type flash memory includes the stacked multiple chips. Each of the chips includes: a readout part performing the continuous readout; an output buffer part outputting data readout from the readout part to input/output bus synchronously with a clock signal; and a final page detecting part detecting if readout pages are the final pages of the chips. The output buffer part responds to a detecting result of the final pages under a condition of performing the continuous readout between the chips. After outputting the data of the final pages through a first output buffer with a large driving capability, outputs or holds the data of the final pages through a second output buffer with a little driving capability.

A data transmission circuit and method, and a storage device are provided. The data transmission circuit includes a serial-parallel conversion module, a comparison module, a data conversion module and a write circuit module. The serial-parallel conversion module receives a plurality of pieces of external data in batches and outputs initial parallel data according to the external data. The comparison module compares the received initial parallel data with global data to output a comparison result. The data conversion module, responsive to that the comparison result indicates that the preset threshold is exceeded, inverts the initial parallel data and transmits the inverted data to a data bus, and responsive to that the comparison result indicates that the preset threshold is not exceeded, transmits the initial parallel data to the data bus. The write circuit module transmits data on the data bus to a global data bus.

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.

A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.

Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.