The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Apparatuses for providing pads included in external terminals of a semiconductor device are described. An example apparatus includes a memory cell array, a data queue (DQ) circuit, a data pad and a power pad. The memory cell array may include one or more memory cells. In a write operation, the data pad receives write data and provides the write data to the DQ circuit. The DQ circuit receives the write data and provides the write data to the memory cell array. In a read operation, the DQ circuit receives read data from the memory cell array and provides the read data. The data pad receives the read data from the DQ circuit and provides the read data. The power pad provides a power supply voltage. The data pad and the power pad are disposed across from each other with respect to the DQ circuit.

In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

A semiconductor device includes a gate signal generator to receive a first clock signal and to generate a first gate signal and a second gate signal based on the first clock signal; a gating clock signal generator to receive a second clock signal and to generate a first gating clock signal, a second gating clock signal and a third gating clock signal based on the first and second gate signals from the gate signal generator and the second clock signal; a data sampler to receive a third clock signal from the gating clock signal generator and to sample an input serial data signal based on the third clock signal; and a deserializer to generate a parallel data signal by deserializing the input serial data signal based on at least one of the first, second, and third gating clock signals from the gating clock signal generator.

Provided is a SoC, a memory device, an electronic device and a method for storing data in an electronic device. The electronic device comprises a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.

A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of the data register. When the data register includes a boundary-lock pattern or a special symbol, the boundary detector outputs a starting address that the boundary-lock pattern or the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.