Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

A pseudo-dual-port memory (PDPM) is disclosed that includes a first memory array bank and a second memory array bank of a plurality of memory array banks. The PDPM also includes parallel pin control logic circuitry configured to perform operations including taking a clock signal, a memory enable signal for a first port, a memory enable signal for a second port, a parallel pin control signal, and address signals for the first and the second memory array banks as inputs and generating a first internal clock and a second internal clock for performing operations corresponding to the first and the second memory array banks at the first port and the second port. A total number of memory array banks may be up to eight memory array banks and each including either a six-transistors (6-T) SRAM bit-cell or an eight-transistors (8-T) SRAM bit-cell in static random access memory architecture.

An example memory sub-system includes: a plurality bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each bank group; and a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving, from a host, a command identifying a row buffer of the plurality of row buffers; and perform an operation with respect to the identified row buffer.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

An imaging device includes a first memory configured to perform writing to multiple addresses thereof by designating the multiple addresses on address-by-address basis, a second memory configured to perform writing simultaneously to multiple address thereof, and a control circuit that controls readout of signals from the first memory and the second memory. The control circuit is configured to perform a first operation mode to sequentially designate the multiple addresses of the first memory and sequentially perform readout of signals from the multiple addresses of the first memory, and a second operation mode to sequentially designate the multiple addresses of the second memory and sequentially perform readout of signals from the multiple addresses of the second memory so that an output value from the second memory becomes the same as a value expected as an output value from the first memory in the first operation mode.

Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.