Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

A vehicle information communication system includes a vehicle device and a center device. The center device includes a storage unit, a center computer, and a center-device communication unit. The storage unit stores memory structure information for each of the ECUs. The memory structure information indicates whether a corresponding memory has a memory structure that supports Read While Write (RWW) operation defined as having a plurality of physically independent memory regions. The center computer is programmed to generate specification data including the memory structure information for each of the at least one target ECUs. The vehicle device includes a vehicle computer. The vehicle computer is programmed to perform the program data rewrites of the at least one target ECU according to the memory structure information included in the specification data.

A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal. Column addresses corresponding to the target columns included in the target row are not consecutive.

A memory system includes a non-volatile memory having a plurality of memory cells, and a controller configured to carry out write operations in a first mode in which n-bit data is written per target memory cell of the non-volatile memory until an allowable data amount of data items has been written, and then, in a second mode in which m-bit data is written per target memory cell of the non-volatile memory, where n is an integer of one or more and m is an integer greater than n. The controller is further configured to detect that an idle state, in which a command has not been received from the host, has continued for a threshold period of time or more, increase the allowable data amount in response thereto, and after the increase, carry out a write operation to write data items in the non-volatile memory in the first mode.

A vehicle information communication system includes a vehicle device and a center device. The center device includes a storage unit, a center computer, and a center-device communication unit. The storage unit stores memory structure information for each of the ECUs. The memory structure information indicates whether a corresponding memory has a memory structure that supports Read While Write (RWW) operation defined as having a plurality of physically independent memory regions. The center computer is programmed to generate specification data including the memory structure information for each of the at least one target ECUs. The vehicle device includes a vehicle computer. The vehicle computer is programmed to perform the program data rewrites of the at least one target ECU according to the memory structure information included in the specification data.

A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.