An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.

The present disclosure includes apparatuses and methods related to modifying an operating mode in memory. An example apparatus can include a memory array and a controller coupled to the memory array, wherein the controller includes a register configured to receive a mode register write command and write a value indicative of an operating mode in which the apparatus has reduced power consumption relative to a normal operating mode.

A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

A semiconductor memory device includes a plurality of input-output pins configured to communicate with a memory controller, a command control logic, a temperature measurement circuit and an operation limit controller. The command control logic controls an operation of the semiconductor memory device based on command signals and control signals transferred from the memory controller through control pins among the plurality of input-output pins. The temperature measurement circuit measures an operation temperature of the semiconductor memory device to generate a temperature code corresponding to the operation temperature. The operation limit controller, when it is determined based on the temperature code that the operation temperature exceeds a risk temperature, controls an internal operation of the semiconductor memory device regardless of the command signals and the control signals transferred from the memory controller to thereby decrease a power consumption of the semiconductor memory device.

A memory architecture for optimizing leakage currents in standby mode and a method thereof is disclosed. The memory architecture includes a plurality of memory segments configured to operate in one or more modes of operations. The plurality of memory segments includes a plurality of decoder slices. Each of the plurality of decoder slice includes a plurality of wordlines running in the row direction; at least one array power header configured for controlling leakage currents within each of the plurality of decoder slice in the row direction; and a retention header. Each of the plurality of power supply rails running in the column direction are segmented within one or more decoder slice to form one or more segmented power supply node.

The semiconductor device 1 comprises a processor 2, a memory connected to the processor and a control circuit, and comprises an active operation mode and a standby operation mode. The memory comprises a normal mode and a RS mode lower power consumption than the normal mode. The memory comprises SRAMs 7_0 to 7_5 which includes a mode terminal RS_T supplied with mode instruction signals RS1_0 to RS1_5 specifying the normal mode or the RS mode, respectively. The control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_0 to 7_2 in transition period which the semiconductor device transitions from the standby operation mode to the active operation mode. And the control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_3 to 7_5 after transition to the active operation mode.

A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

This document describes apparatuses and techniques for termination of a pulse amplitude modulation signal of a memory circuit. In various aspects, a memory circuit is implemented with a termination circuit that includes a power rail, a resistor, and a switch to couple the resistor between the power rail and a signal line of a memory interconnect. The power rail may be configured to provide power at a termination voltage that is nominally half of a voltage of another power rail from which a corresponding transmission circuit operates. This may be effective to enable termination of pulse amplitude modulation signals to the termination voltage instead of a higher voltage that corresponds to the power rail of the transmission circuit or a ground-referenced node. By so doing, use of the termination circuit may reduce power consumption and/or improve signal integrity of the memory circuit.

An electronic device includes at least one processor, a Universal Flash Storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including a plurality of downstream lanes for transmitting data and a plurality of upstream lanes for transmitting data and storage including a cache memory and a plurality of non-volatile memories. The at least one processor transmits a first control signal to instruct measuring a temperature of the storage and identifying of the measured temperature exceeding a threshold value to the UFS device controller, receives a status signal indicating that the measured temperature exceeds the threshold value from the UFS device controller, and based on the status signal, transmits, to the UFS device controller, a second control signal to instruct that deactivating at least some of the plurality of downstream lanes and upstream lanes, or deactivating the cache memory in the storage.