A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

Various embodiments include a memory device that is capable of performing memory access operations with reduced power consumption relative to prior approaches. The memory device receives early indication as to whether a forthcoming memory access operation is a read operation or a write operation. The memory device enables various circuits and disables other circuits depending on whether this early indication identifies an upcoming memory access operation as a read operation or a write operation. As a result, circuits that are not needed for an upcoming memory access operation are disabled earlier during the memory access operation relative to prior approaches. Disabling such circuits earlier during the memory access operation reduces power consumption without reducing memory device performance.

An information processing apparatus includes a first processor that executes a hardware startup process, a second processor separate from the first processor, and a memory interface which includes a temperature sensor, the memory interface being configured to interface with a memory, wherein the memory interface is configured to, when a temperature sensed by the temperature sensor reaches a predetermined temperature threshold value, throttle performance of the memory, the first processor executing the hardware startup process includes transmitting a plurality of temperature threshold values to the memory interface via a first interface, and the second processor, in response to an event, transmits selection information to the memory interface via a second interface different from the first interface, the selection information indicating selection of one of the plurality of temperature threshold values to be set as the predetermined temperature threshold value.

Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

A sense amplifying device includes a bit line bias voltage adjuster and a sense amplifying circuit. The bit line bias voltage adjuster receives a power voltage to be an operation voltage. The bit line bias voltage adjuster includes a first amplifier, a first transistor and a first current source. The first amplifier, based on the power voltage, generates an adjusted reference bit line voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage, wherein the first transistor is a native transistor. The sense amplifying circuit receives the power voltage to be the operation voltage, and generates a sensing result according to the adjusted reference bit line voltage.

Circuits and methods are described herein for controlling a bit line precharge circuit. For example, a control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first light sleep signal. The first latch circuit generates a second light sleep signal according to a clock signal. The second latch circuit is configured to receive the second light sleep signal. The second latch circuit generates a third light sleep signal according to a sense amplifier enable signal. The second latch circuit provides the third light sleep signal to a bit line reading switch, so the bit line reading switch is cutoff after a sense amplifier is enabled.

A storage device is provided. The storage device includes a memory device including a memory cell array configured to store metadata and main data and a storage controller configured to access the memory device and control the memory device, wherein the storage controller is configured to read data from the memory device at a speed adaptively varying to a first read speed or a second read speed according to a state of the memory device, the second read speed being faster than the first read speed.

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.