Methods, systems, and devices related to page policies for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may be configured to receive a read command for data stored in the memory array and transfer the data from the memory array to the signal development cache. The memory device may be configured to sense the data using an array of sense amplifiers. The memory device may be configured to write the data from the signal development cache back to the memory array based on one or more policies.

A memory circuit comprises an array of data storage elements; access circuitry to access a data bit, stored by a data storage element enabled for access, by an access signal for that data storage element; and control circuitry to enable groups of data storage elements for access, the groups having a group size, the group size being one or more, the access signals for data storage elements in a group being combined to provide a combined access signal common to that group of data storage elements; the control circuitry being configured to selectively operate in at least a first mode and a second mode, the group size in the first mode being different to the group size in the second mode.

According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of sub arrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

An operating method of a memory system includes storing normal data to a first storage area of a non-volatile memory in a first program mode among multiple program modes defined according to a number of bits stored in each memory cell; storing dummy data in the first storage area in at least one of the multiple program modes including the first program mode; and copying the normal data from the first storage area to a second storage area of the non-volatile memory based on dummy data stored in the first program mode.

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions.

A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.