A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

A media management operation to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system that is at a higher data density than the cache memory a write request to program data to a memory device of a memory sub-system is executed. An entry of a first data structure identifying a page count corresponding to the source block of the cache memory is generated. Following a determination that the data is written to the set of pages of the destination block of the storage area, the entry is updated to identify a decreased page count corresponding to the source block, where the data is erased from the source block when the decreased page count satisfies a condition. A second entry of a second data structure including information mapping a logical block to the source block of the cache memory is also updated.

A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data.

Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in high-bandwidth memory. The DRAM cache management circuit comprises a DRAM cache indicator cache, which stores master table entries that are read from a master table in a system memory DRAM and that contain DRAM cache indicators. The DRAM cache indicators enable the DRAM cache management circuit to determine whether a memory line in the system memory DRAM is cached in the DRAM cache of high-bandwidth memory, and, if so, in which way of the DRAM cache the memory line is stored. Based on the DRAM cache indicator cache, the DRAM cache management circuit may determine whether to employ the DRAM cache and/or the system memory DRAM to perform a memory access operation in an optimal manner

A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Methods, systems, and devices for fully associative cache management are described. A memory subsystem may receive an access command for storing a first data word in a storage component associated with an address space. The memory subsystem may include a fully associative cache for storing the data words associated with the storage component. The memory subsystem may determine an address within the cache to store the first data word. For example, the memory subsystem may determine an address of the cache indicated by an address pointer (e.g., based on the order of the addresses) and determine a quantity of accesses associated with the data word stored in that cache address. Based on the indicated cache address and the quantity of accesses, the memory subsystem may store the first data word in the indicated cache address or a second cache address sequential to the indicated cache address.