The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.

Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.

According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.

According to one embodiment, a semiconductor storage device includes: a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command; a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command; and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.

Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.