A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.

An apparatus for non-volatile memory, and more specifically a ReRAM device with a buried resistive memory cell. The memory cell includes a first contact disposed on a substrate, an active layer, a second contact, a first diffused zone disposed within the active layer, a second diffused zone disposed within the active layer, and an active switching zone disposed within the active layer in between the first diffused zone and the second diffused zone. In one embodiment, the active zone may be doped by diffusion or ion implantation and/or may be fabricated utilizing a self-aligned process. In another embodiment, the memory cell may combine a deep implant and shallow diffusion well to create the active zone. The vertically and laterally isolated buried resistive memory cell concentrates the electric field away from the edges of the device and eliminates the effects of interface impurities and contaminants.

A programmable logic device according to an embodiment includes: a plurality of first and second wiring lines; a plurality of resistive change elements each including a first electrode containing Ni and connected to corresponding one of the first wiring lines, a second electrode containing TiN and connected to corresponding one of the second wiring lines, a resistive change layer containing a hafnium oxide and arranged between the first electrode and the second electrode, and an insulation layer arranged between the resistive change layer and the second electrode, the insulation layer including at least one of an aluminum oxide, an iron oxide, a titanium oxide, a copper oxide, a nickel oxide, a tantalum oxide, a tungsten oxide, a chromium oxide, a rhenium oxide, and a hafnium oxynitride.

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F.sup.2 or less density.

A switch element includes a first wiring line that is provided in a first insulating film and extends in a first direction; a second wiring line that is provided in a second insulating film and extends in a second direction that intersects the first direction; an ion conductive layer sandwiched between the first wiring line and the second wiring line and directly in contact with the second wiring line in an intersection region where the first wiring line and the second wiring line intersect, and enabled to conduct metal ions supplied from the second wiring line; and a metal oxide film sandwiched between the first wiring line and the ion conductive layer.

Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

A system may include a multi-lead memristor. The multi-lead memristor may include a first lead, a second lead, a third lead, a first memristor material, and a second memristor material. The second lead may be positioned between the first lead and the third lead. The first memristor material may be positioned between the first lead and the second lead. The second memristor material may be positioned between the second lead and the third lead.

A system may include an array of interconnected memristors. Each memristor may include a first electrode, a second electrode, and a memristor material positioned between the first electrode and the second electrode. The system may further include a controller communicatively coupled to the array of interconnected memristors. The controller may be configured to tune the array of interconnected memristors.