A two-terminal memory device and methods for its use are provided. In the device, a bottom electrode is electrically continuous with a first operating terminal, and a control gate electrode is electrically continuous with a second operating terminal. A stack of insulator layers comprising a hopping conduction layer and a tunnel layer is contactingly interposed between the bottom electrode and the control gate electrode. The tunnel layer is thinner than the hopping conduction layer, and it has a wider bandgap than the hopping conduction layer. The hopping conduction layer consists of a material that supports electron hopping transport.

Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in electrical communication with the first terminal and the second terminal, wherein the voltage difference between the first terminal and the second terminal changes the channel from a first state to a second state when a threshold voltage between the first terminal and the second terminal is exceeded, the threshold voltage being dependent on temperature. The third terminal is resistive and receives a control signal to apply heat to the pillar and modulate the threshold voltage. The switching device can be used to select the memory stack through the bitline and provide a nearly limitless current based on the threshold switching conduction providing avalanche current conduction through the switching device.

A phase change memory apparatus comprises at least one heating layer; and at least one phase change layer comprising a vanadium dioxide layer, wherein each of the at least one phase change layer is set corresponding to each of the at least one heating layer, the at least one heating layer is configured to heat the at least one phase change layer.

Technologies relating to improving LRS data retention and reliability in RRAM-based crossbar array circuits are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive a switching voltage being applied to the filament forming layer. The filament forming layer may be made of one of the following materials: HfOxSiy, HfOxNy, HfOxAly, HfOx doped with SiO2, HfOx doped with Al2O3, HfOx doped with N, HfOx doped with Si.sub.3N.sub.4, HfOx doped with AlN, or a combination thereof. The bottom electrode or the top electrode may be made of one of the following materials: Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, Ru, TaN, NbN, a combination therefore, or an alloy with other electrically conductive materials.

A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.

There are provided a variable resistance memory device and an operating method thereof. In a method for operating a variable resistance memory device, the method includes programming multi-bit data in a multi-bit variable resistance memory cell of the variable resistance memory device, wherein the programming includes: generating sequentially increased program voltage pulses, based on the multi-bit data; and applying the program voltage pulses to the multi-bit variable resistance memory cell, wherein a current-voltage curve of the multi-bit variable resistance memory cell exhibits a self-compliance characteristic, wherein the program voltage pulses are included in a voltage section having the self-compliance characteristic.

In some examples, a hybrid memory device includes multiple memory cells, where a given memory cell of the multiple memory cells includes a volatile memory element having a plurality of layers including electrically conductive layers and a dielectric layer between the electrically conductive layers, and a non-volatile resistive memory element to store different data states represented by respective different resistances of the non-volatile resistive memory element, the non-volatile resistive memory element having a plurality of layers including electrically conductive layers and a resistive switching layer between the electrically conductive layers of the non-volatile resistive memory element.

According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.