A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each including a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable resistors in the array with resistances corresponding to values of a weight factor W.sub.mn for the corresponding cell. Alternatively, the resistances can be programmed during manufacture. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs X.sub.m to rows m. Column drivers are configured to apply currents I.sub.n to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.

A memory structure for use in a memory device comprising at least one first layer and at least one second layer: the at least one first layer comprises a plurality of a first element, and the at least one second layer comprises a plurality of a second element; and, wherein the memory structure has an electrical resistive state that can be changed in response to an electromotive force being applied thereto.

Described is a memory cell which comprises: a transistor positioned in a backend of a die, the transistor comprising: a source structure and a drain structure; a gate structure between the source structure and the drain structure; a source contact coupled to and above the source structure and a drain contact coupled to and below the drain structure; and a Resistive Random Access Memory (RRAM) device coupled to the drain contact.

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

This invention relates to memory resistors, arrays of memory resistors and a method of making memory resistors. In particular, this invention relates to memory resistors having an on state and an off state, comprising: (a) a first electrode; (b) a second electrode; (c) a dielectric layer disposed between the first and second electrodes; wherein the dielectric layer comprises nanoparticles of semiconductor material, and wherein in the on state nanoparticles form at least one conductive filament encapsulated by the dielectric layer, thereby providing a conductive pathway between the first electrode and the second electrode.

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

According to one embodiment, a semiconductor memory device includes a word line, a bit line crossing the word line, a memory cell, and a controller. The memory cell is provided at an intersection between the word and bit lines and includes a variable resistive element. The controller controls a voltage application and a read operation to the memory cell. The controller performs a first operation of applying a first voltage to the memory cell, and a first verification of verifying whether a resistance of the memory cell becomes equal to a first value or greater after the first operation. The controller performs a second operation of applying to the memory cell a second voltage set based on the first voltage, when the resistance of the memory cell becomes equal to the first value or greater in the first verification.

A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each including a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable resistors in the array with resistances corresponding to values of a weight factor W.sub.mn for the corresponding cell. Alternatively, the resistances can be programmed during manufacture. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs X.sub.m to rows m. Column drivers are configured to apply currents I.sub.n to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.