A crested barrier memory and selector device may include a first electrode, a first self-rectifying, tunneling layer having a first dielectric constant, and an active, barrier layer that has a second dielectric constant and another self-rectifying, tunneling layer having a third dielectric constant. The first self-rectifying layer may be between the first electrode and the active layer. The second dielectric constant may be at least 1.5 times larger than the first dielectric constant. The device may also include a second electrode, where the active, barrier layer is between the first self-rectifying, tunneling layer and the second electrode.

A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

A memory cell includes a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer is maintained in an amorphous state during a program operation.

A crested barrier memory and selector device may include a first electrode, a first self-rectifying, tunneling layer having a first dielectric constant, and an active, barrier layer that has a second dielectric constant and another self-rectifying, tunneling layer having a third dielectric constant. The first self-rectifying layer may be between the first electrode and the active layer. The second dielectric constant may be at least 1.5 times larger than the first dielectric constant. The device may also include a second electrode, where the active, barrier layer is between the first self-rectifying, tunneling layer and the second electrode.

Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and encapsulating the MIM stack of an RERAM cell to control the oxygen content in the memory cell dielectric of the RERAM cell. According to one embodiment, a non-oxygen-containing dielectric encapsulation layer is deposited onto the MIM stack in-situ while the substrate remains within the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the encapsulation layer within the same processing chamber, the techniques described herein minimize the exposure of the memory cell dielectric to oxygen, while maintaining throughput.

A nonvolatile resistive switching memory comprising an insulating substrate, a lower electrode, a lower graphene barrier layer, a resistive switching functional layer, an upper graphene barrier layer, and an upper electrode, wherein the lower and/or the upper graphene barrier layer is/are capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer under an applied electric field. According to the nonvolatile resistive switching memory device of the present invention and manufacturing method thereof, a monolayer or multilayer graphene film as a metal ions/atoms barrier layer is inserted between the upper/lower metal electrode and the resistive switching functional layer, which is capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer during the programming or erasing process of the resistive switching device, thereby improving the reliability of the device.

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.