A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

A high temperature resistant memristor comprises a bottom electrode, a dielectric and a top electrode, wherein the dielectric is a two-dimensional covalent crystal material or a two-dimensional covalent crystal material doped with oxygen or sulfur which has (1) the two-dimensional covalent crystal material or the two-dimensional covalent crystal material doped with oxygen or sulfur is adopted as the dielectric; (2) a memristor prepared by utilizing relatively high thermal stability of a lattice structure of two-dimensional transition metal; and (3) the high temperature resistant memristor.

A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 110-4 ohm-m.

Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector device has a positive threshold voltage and a negative threshold voltage, and a magnitude of the positive threshold voltage is different from a magnitude of the negative threshold voltage.

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer disposed between the first and second conductive layers. The variable resistance layer includes a first layer containing a semiconductor or a first metal oxide, a second layer disposed between the first layer and the first conductive layer, and containing a second metal oxide, and a first amorphous layer disposed between the second layer and the first conductive layer.

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.