An apparatus is described that includes a resistive random access memory cell having a word line that is to receive a narrowed word line signal that limits an amount of time that an access transistor is on so as to limit the cell's high resistive state and/or the cell's low resistive state. Another apparatus is described that includes a resistive random access memory cell having SL and BL lines that are to receive respective signals having different voltage amplitudes to reduce source degeneration effects of the resistive random access memory cell's access transistor. Another apparatus is described that includes a resistive random access memory cell having a storage cell comprising a bottom-side OEL layer. Another apparatus is described that includes a resistive random access memory cell having a storage cell within a metal layer that resides between a pair of other metal layers where parallel SL and BL lines of the resistive random access memory cell respectively reside.

Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.

An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.

A low voltage forming NVM structure including a plurality of ReRAM devices arranged in a cross bar array and sandwiched between a plurality of first electrically conductive structures and a plurality of second electrically conductive structures. Each first electrically conductive structure is oriented perpendicular to each second electrically conductive structure. The plurality of second electrically conductive structures includes a first set of second electrically conductive structures having a first top trench area A1, and a second set of second electrically conductive structures having a second top trench area A2 that is greater than A1. Each second electrically conductive structure of the first set contacts a surface of at least one of the first electrically conductive structures, and each second electrically conductive structure of the second set contacts a top electrode of at least one of the ReRAM devices.

Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

A true random number generator device based on a diffusive memristor is disclosed. The random number generator device includes a diffusive memristor driven by a pulse generator circuit. The diffusive memristor produces a stochastically switched output signal. A comparator circuit receives the stochastically switched output signal from the diffusive memristor and generates an output signal having a random pulse width. An AND gate logic circuit is driven by a clock signal and the output signal from the comparator circuit. The AND gate logic circuit produces a combined output signal. A counter circuit receives the combined output signal from the AND gate logic circuit and generates a random bit string output signal.

A semiconductor memory device includes a substrate, a first conductive line disposed on the substrate and extending in a first direction, a second conductive line disposed on the first conductive line, and extending in a second direction intersecting the first direction, and a memory cell disposed between the first conductive line and the second conductive line, wherein the memory cell includes, a first electrode connected to the first conductive line, a second electrode connected to the second conductive line, an OTS film disposed between the first electrode and the second electrode, a high-concentration electrode disposed between the second electrode and the OTS film, wherein a concentration of nitrogen contained in the second electrode is lower than a concentration of nitrogen contained in the high-concentration electrode, wherein a logic state of data stored in the OTS film is based on a polarity of a program voltage.

A storage device of an embodiment of the present disclosure includes: a first electrode; a second electrode; a storage layer provided between the first electrode and the second electrode and including at least copper, aluminum, zirconium, and tellurium; and a barrier layer provided between the storage layer and the second electrode and including zirconium at a higher concentration than at least the storage layer, the barrier layer having a copper concentration, at an interface with the second electrode, being lower than the storage layer.