Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

The present disclosure relates to a chalcogenide material including germanium (Ge) with a first atomic percent, selenium (Se) with a second atomic percent that is at least twice the first atomic percent of the germanium, and indium (In) with a third atomic percent less the first atomic percent of the germanium.

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.

The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more of the plurality of memory cells. The method involves detecting electrical responses of the one or more memory cells to the first voltage and the second voltage. The method also involves determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

The present invention discloses a three-dimensional vertical read-only memory (3D-OTP.sub.V). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming.