A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.

The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A.sub.1, a 1T1R crossbar A.sub.2, a 1T1R crossbar A.sub.3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.

A memory device includes a data memory array, a reference memory array and a detection circuit. The reference memory array includes (N/2+1) bit lines, (N/2) source lines and reference cells, N being a positive even integer. Each row of reference cells includes a (2n−1)th reference cell and a (2n)th reference cell. The (2n−1)th reference cell includes a first terminal coupled to an nth bit line, and a second terminal coupled to an nth source line, n being a positive integer less than N/2+1. The (2n)th reference cell includes a first terminal coupled to an (n+1)th bit line, and a second terminal coupled to the nth source line. The detection circuit compares a data current outputted from the data memory array and a reference current outputted from the reference memory array to determine a data state of a memory cell.

A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration.

A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

A phase-change material having specific SiO.sub.x doping into special Ge-rich Ge.sub.xSb.sub.yTe.sub.z material is described. Integrated circuits using this phase-change material as memory elements in a memory array can pass the solder bonding criteria mentioned above, while exhibiting good set speeds and demonstrating good 10 year data retention characteristics. A memory cell described herein comprises a first electrode and a second electrode; and a memory element in electrical series between the first and second electrode. The memory element comprises a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %.

A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.

A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.