High thermal stability SiO.SUB.x .doped GeSbTe materials suitable for embedded PCM application

Abstract

A phase-change material having specific SiO.sub.x doping into special Ge-rich Ge.sub.xSb.sub.yTe.sub.z material is described. Integrated circuits using this phase-change material as memory elements in a memory array can pass the solder bonding criteria mentioned above, while exhibiting good set speeds and demonstrating good 10 year data retention characteristics. A memory cell described herein comprises a first electrode and a second electrode; and a memory element in electrical series between the first and second electrode. The memory element comprises a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %.

Claims

1. A memory device, comprising: a first electrode and a second electrode; a memory element in electrical series between the first and second electrode, comprising a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %, and a buffer layer between the phase change material and at least one of the first and second electrodes.

2. The device of claim 1, wherein the combination of elements includes Ge, Sb, Te, Si and O in amounts effective to have a crystallization transition temperature in excess of 250° C.

3. The device of claim 1, wherein the combination of elements includes Ge, Sb, Te, Si and O in amounts effective to have a set speed less than 1000 ns.

4. The device of claim 1, wherein the Ge is in a range of 29 to 32 at %.

5. The device of claim 1, wherein the Ge is in a range of 29 to 32 at %, the Sb is in a range of 15 to 16 at %, and the Te is in a range of 27 to 31 at %.

6. An integrated circuit comprising: an array of memory cells having memory elements arranged in series between access lines, memory cells in the array comprising a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %, and a buffer layer between the phase change material and at least one of the access lines.

7. The integrated circuit of claim 6, wherein the combination of elements includes Ge, Sb, Te, Si and O in amounts effective to have a crystallization transition temperature in excess of 250° C.

8. The integrated circuit of claim 6, wherein the combination of elements includes Ge, Sb, Te, Si and O in amounts effective to have a set speed less than 1000 ns.

9. The integrated circuit of claim 6, wherein the combination of elements includes Ge, Sb, Te, Si and O in amounts effective to retain data stored in the memory elements of the array after exposure to 260° C. for 30 seconds.

10. The integrated circuit of claim 6, wherein the array is an embedded memory, and including logic on the integrated circuit configured to utilize the array to store data.

11. The integrated circuit of claim 6, wherein Ge is in a range of 29 to 32 at %.

12. The integrated circuit of claim 6, wherein the Ge is in a range of 29 to 32 at %, the Sb is in a range of 15 to 16 at %, and the Te is in a range of 27 to 31 at %.

13. The integrated circuit of claim 6, wherein the array is pre-coded with data before mounting the integrated circuit on a patterned circuit substrate.

14. A data processing device, comprising: an integrated circuit solder bonded to a patterned circuit substrate, wherein the integrated circuit comprises an array of memory cells arranged in series between access lines, memory cells in the array having memory elements comprising a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %, and a buffer layer between the phase change material and at least one of the access lines.

15. The data processing device of claim 14, wherein the combination of elements includes Ge, Sb, Te, Si and O in amounts effective to have a set speed less than 1000 ns.

16. The data processing device of claim 14, further including at least one additional integrated circuit solder bonded to the patterned circuit substrate.

17. The data processing device of claim 14, wherein the array is an embedded memory, and including logic on the integrated circuit configured to utilize the array to store data.

18. The data processing device of claim 14, wherein the Ge is in a range of 29 to 32 at %.

19. The data processing device of claim 14, wherein the Ge is in a range of 29 to 32 at %, the Sb is in a range of 15 to 16 at %, and the Te is in a range of 27 to 31 at %.

20. The data processing device of claim 14, wherein the array is pre-coded with data before solder bonding to the patterned circuit substrate.

21. A method for manufacturing a data processing device, comprising: storing data in an array of memory cells on an integrated circuit, the array of memory cells having memory elements arranged in series between access lines, memory cells in the array comprising a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at % and a buffer layer between the phase change material and at least one of the access lines; and after storing the data, solder bonding the integrated circuit to a patterned circuit substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates structure of a “mushroom” type memory element including a memory element comprising SiO.sub.x doped Ge-rich Ge.sub.xSb.sub.yTe.sub.z material.

(2) FIG. 2 illustrates an “active in via” type memory element structure including a memory element comprising SiO.sub.x doped Ge-rich Ge.sub.xSb.sub.yTe.sub.z material.

(3) FIG. 3 illustrates structure of a cross-point memory cell with a memory element including a memory element comprising SiO.sub.x doped Ge-rich Ge.sub.xSb.sub.yTe.sub.z material.

(4) FIG. 4 illustrates structure of a “pore” type memory element including a memory element comprising SiO.sub.x doped Ge-rich Ge.sub.xSb.sub.yTe.sub.z material.

(5) FIG. 5 diagrammatically illustrates stages in an example of constructing an assembly of semiconductor chips including a pre-coded chip on a circuit board or other substrate.

(6) FIGS. 6A and 6B illustrate stages in a surface mount operation suitable for integrated circuits described herein.

(7) FIG. 7 shows examples of reflow heating schedules for a conventional solder (broken line) and for a lead-free SnAg solder.

(8) FIG. 8 is a graph of temperature versus resistivity, illustrating the crystallization transition temperature for Materials A-D.

(9) FIG. 9 is a graph of baking time at various temperatures versus failure rate for Material A.

(10) FIG. 10 is a graph illustrating results of endurance testing of Material A.

(11) FIG. 11 is a graph of baking time at various temperatures versus failure rate for Material C.

(12) FIG. 12 is a graph illustrating results of endurance testing of Material C.

(13) FIGS. 13 and 14 are graphs of resistance distribution in a memory array on an integrated circuit before and after baking according to solder bonding criterion testing for Material A.

(14) FIGS. 15 and 16 are graphs of resistance distribution in a memory array on an integrated circuit before and after baking according to solder bonding criterion testing for Material C.

(15) FIG. 17 is a simplified block diagram of an integrated circuit memory device including phase change memory cells as described herein.

(16) FIG. 18 is a simplified flowchart of a manufacturing process described herein.

(17) FIG. 19 is a schematic diagram of an array of one transistor/one memory element memory cells including buffer layers as described herein.

DETAILED DESCRIPTION

(18) A detailed description of embodiments of the present disclosure is provided with reference to the FIGS. 1-19. A new class of phase change material is described which comprises a silicon oxide doped, Ge-rich GST. The term “doped” as used herein refers to additives combined with the GST in amounts effective to achieve desirable changes in characteristics of GST not including the additive.

(19) Representative materials in the class include materials A-D identified the following table.

(20) TABLE-US-00001 [Ge] at. % [Sb] at. % [Te] at. % [Si] at. % [O] at. % Material A 30.1 ± 0.5 15.8 ± 5 30.7 ± 5 8.4 ± 0.5 15.0 ± 2 Material B 30.7 ± 0.5 14.7 ± 5 26.5 ± 5 7.7 ± 0.5 20.4 ± 2 Material C 31.4 ± 0.5 15.1 ± 5 27.9 ± 5 8.9 ± 0.5 16.7 ± 2 Material D 34.9 ± 0.5 14.0 ± 5 26.3 ± 5 7.6 ± 0.5 17.2 ± 2

(21) The new class of materials are a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %.

(22) Examples of the material of the memory elements are described in which Ge is in a range of 29 to 32 at %. Examples are also described in which the Ge is in a range of 29 to 32 at %, the Sb is in a range of 15 to 16 at %, and the Te is in a range of 27 to 31 at %.

(23) FIG. 1 illustrates a “mushroom” type memory element 100 having a first electrode 120 extending through dielectric 130, comprising a memory element 110 of silicon oxide doped, Ge-rich GST phase change material, a buffer 111, in the form of a continuous layer, in this embodiment contacting the memory element 110, and a second electrode 140 on the memory element 110. The first electrode 120 contacts the memory element of phase change material over a first contact area 122, and the second electrode contacts the carbon deposit over a second contact area 141. In a mushroom type memory element, as illustrated, the first contact area 122 is smaller than the second contact area 141, such as at least 50% smaller, and in some embodiments at least 90% smaller. The first electrode 120 is coupled to a terminal of an access device (not shown) such as a diode or switch, while the second electrode 140 is coupled to a bit line and can be part of the bit line (not shown). The small first contact area 122, between the memory element of phase change material and the first electrode 120, and a relatively larger second contact area 141 between the carbon deposit 111 and the second electrode 140, results in higher current densities with small absolute current values in an active region of the memory element 110 proximal to the first electrode 120. In one example configuration, the first electrode 120 has a first contact area 122 on the order of 15 to 30 square nanometers, while the second electrode may have a contact area 141 that is continuous along a conductive line, acting as a bit line or local bit line, with the memory element of phase change material formed so as to line the bottom side of the conductive line continuously along a length that of the conductive line, with first electrodes (like 120) of a plurality of mushroom memory elements contacting the memory element distributed along the length.

(24) The buffer layer 111 can be a sputter deposited formation having a thickness less than 15 nm, such as about 10 nm, contacting the memory element of phase change material. The buffer layer can comprise carbon, carbon silicide, titanium nitride or other suitable buffer layer materials.

(25) The memory element of phase change material can have a thickness in the region of the first contact area 122 selected according to operating characteristics of the particular materials, and can be on the order of 50 nm, for example. The thickness of the phase change material depends on the design and operating conditions of the cell structure.

(26) The first and second electrodes 120, 140 may comprise, for example, TiN or TaN. Alternatively, the first and second electrodes 120, 140 may each be W, WN, TiAlN or TaAlN, or comprise, for further examples, one or more elements selected from the group consisting of doped-Si, Si, C, Ge, Cr, Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru and combinations thereof.

(27) In the illustrated embodiment the dielectric 130 comprises silicon nitride. Alternatively, other dielectric materials, such as silicon oxides, may be used.

(28) The contact area 122 between the first electrode 120 and the memory element 110 of phase change material has a width (which in some embodiments is a diameter) less than that of the contact area 141 between the memory element 110 of phase change material and the second electrode 140. Thus, current is concentrated in the portion of the memory element 110 proximal to or adjacent the first electrode 120, resulting in the active region in which the phase change kinetics are confined during operation.

(29) The first electrode 120 extends through dielectric 130 to underlying access circuitry (not shown). The underlying access circuitry can be formed by standard processes as known in the art, and the configuration of elements of the access circuitry depends upon the array configuration in which the memory cells described herein are implemented. Generally, the access circuitry may include access device switches, such as Ovonic threshold switches, FET transistors or bipolar transistors. Also, access devices such as diodes can be utilized. Other elements of access circuitry include word lines and sources lines, conductive plugs, and doped regions used as conductors within a semiconductor substrate.

(30) FIG. 2 illustrates a cross-sectional view of a pillar-shaped memory element having an “active in via” structure. The memory element includes a memory element 210 of phase change material between first and second electrodes 212, 211, with a buffer 215 formed between the memory element 210 of silicon oxide doped, Ge-rich GST phase change material and the second electrode 211. The memory element has a width substantially the same, in this example, as that of the first and second electrodes 212, 211 to define a multi-layer pillar surrounded by dielectric (not shown), in operation, as current passes between the first and second electrodes 212, 211 through the carbon deposit 215 and the memory element 210.

(31) FIG. 3 illustrates an example memory cell 325 which comprises a multi-layer pillar disposed in the cross-point of a first access line 310 and a second access line 320.

(32) The pillar in this example includes a bottom electrode layer 301, such as a metal, metal nitride, a doped semiconductor, or the like, on the first access line 310.

(33) A buffer layer 302 is disposed on the bottom electrode layer 301. In some embodiments, the buffer layer 302 can be a composition such as carbon, or a combination of silicon and carbon. The buffer layer 302 can be, for example, 15 to 30 nm thick.

(34) An OTS switching layer 303 is disposed on the buffer layer 302. The OTS switching layer 303 can comprise an OTS material such as, for some examples, AsSeGeSi, AsSeGeSiC, AsSeGeSiN, AsSeGeSiTe, AsSeGeSiTeS, AsTeGeSi, AsTeGeSiN, and other available OTS materials. The OTS switching layer can be for example, 15 to 45 nm thick, and preferably less than 50 nm thick.

(35) A buffer layer 304 is disposed on the OTS switching layer 303, and can be called a capping layer for the OTS material. The buffer layer 304 can be a barrier layer that comprises a composition of silicon and carbon. The buffer layer 304 can be, for example, 15 to 30 nm thick.

(36) A memory element 305 is disposed on the buffer layer 304. The material of the memory element comprises a silicon oxide doped, Ge-rich GST phase change memory material.

(37) The memory element 305 can be a layer having a thickness selected according to the particular embodiment.

(38) A buffer 306 is disposed on a top surface of the memory element 305. The buffer 306 can be, for example, a continuous layer of carbon or other material, 5 to 15 nm thick.

(39) The first access lines (bit lines) and the second access lines (word lines) can comprise a variety of metals, metal-like materials and doped semiconductors, or combinations thereof. Embodiments of the first and second access lines can be implemented using one or more layers of materials like tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), Tungsten silicide (WSi), TiN/W/TiN, and other materials. For example, the thicknesses of the first access lines and the second access lines can range from 10 to 100 nm. In other embodiments, the first access lines and the second access lines can be very thin, or much thicker. The material selected for the second access lines is preferably selected for compatibility with the carbon deposit 306 in this example, or otherwise with the memory cell 325. Likewise, the material selected for the first access lines is preferably selected for compatibility with the electrode material of the bottom electrode layer 301, or otherwise with the memory cell 325.

(40) In another embodiment, a bottom electrode layer like that shown in FIG. 1 has a smaller contact surface than the surface of the switching layer. As such, an increased current density can be achieved.

(41) FIG. 4 illustrates a cross-sectional view of a fourth memory element having a pore-type structure. The memory element 416 is a body of silicon oxide doped, Ge-rich GST phase change material surrounded by dielectric (not shown) in electrical series between first and second electrodes 420, 440 at top and bottom surfaces, respectively. A buffer 414 is formed on a top surface of the memory element 416 of phase change material as discussed above. The memory element 416 of phase change material can have a width proximal the top electrode 440 that is greater than the width proximal the first electrode 420.

(42) FIG. 5 diagrammatically illustrates stages in an example of constructing an assembly of semiconductor chips on a circuit board or other substrate. In this example, the desired selection of chips, such as a microcontroller unit MCU 12, a silicon oxide doped, Ge-rich GST phase change memory PCM 14, at least part of which can be used for storing code or other data sets, random access memory RAM 16, and an input/output I/O device 18 are “designed in” for an electronic product including a circuit board. The non-volatile memory in one or more of the selected chips can be programmed by a manufacturer as indicated by arrow 11, such as using a program and test system before or after packaging of the individual chips. In this example, the PCM 14 is programmed using a pre-mounting coding process to yield pre-coded PCM 14′. Also, any coding in the other chips can also be carried out at this stage, to yield a collection of pre-coded chips of PCM 14′, adapted for a specific use in the field. The pre-coded chips are thereafter mounted as indicated by arrow 13 onto a circuit board (for example, a motherboard) 15 or other substrate. The procedure used to mount the chips on the substrate can require a thermal cycle that heats the chips, during which the memory cells in the coded PCM can be raised to a temperature above a transition temperature for changes in solid phase of typical phase change memory materials. Also, in some embodiments known as system-on-a-chip SOC devices, a single chip, including an embedded memory including silicon oxide doped, Ge-rich GST phase change memory array and other circuitry, can be used in place of the four devices illustrated in FIG. 5.

(43) A representative mounting procedure that includes a thermal process that can disturb prior art phase change memory cells is discussed with reference to FIGS. 6A, 6B and 7. Stages in a surface mount operation are illustrated in FIGS. 6A and 6B. In the example shown in these Figures, a leadframe package 600 and a flip-chip package 720 are mounted onto and electrically connected to bond sites 623, 723 exposed at a package mount surface of a circuit board 624.

(44) The leadframe package 600 in this example includes a semiconductor die 614, which can be pre-coded as described herein, mounted active side upward on leads 616. Interconnect pads 613 in the die are electrically connected to bond sites on bond fingers 615 on the leads 616 by wire bonds 612. The die, wire bonds, and bond fingers are enclosed in a protective encapsulation 619, constituting a package body from which the leads project. The leads 616 have a dogleg shape, so that the feet 617 are situated below the package body, and some clearance is provided between the lower surface of the package body and the upper surface of the circuit board when the feet 617 of the leads are at rest on the bond sites 623.

(45) The flip-chip package 720 in this example includes a die 714 which can be pre-coded as described herein, mounted in a flip-chip fashion on, and electrically connected to circuitry on, a package substrate 706. Electrically conductive balls or bumps (typically metal, such as gold or solder) 712 are mounted on interconnect pads 713 on the die. Bond pads 705 connected to circuitry in the substrate 706 are exposed at the die attach surface of the substrate to provide bond sites for attachment of the interconnect balls or bumps. Second-level interconnect lands 707 on the opposite side of the substrate are connected to bond pads 705 by way of the circuitry in the substrate. An underfill 719 fills the space between the active side of the die and the die mount side of the package substrate, to complete the package. Solder balls 716 are mounted on the lands 707 to provide for electrical connection of the package 720 to bond sites 723 on the circuit board.

(46) The second-level interconnection of the leadframe package 600 and the flip-chip package 720 is made by soldering the feet 617 and the second-level interconnect solder balls 716 onto the bond sites 623, 723. Typically, prior to mounting the packages, the circuit board is prepared by depositing small amounts of solder or solder paste (for example by plating or printing) on the bond sites (the solder or solder paste may optionally be omitted for flip-chip interconnection). Then, the packages are oriented so that the feet 617 and the solder balls 716 are aligned with corresponding bond sites 623, 723 on the circuit board, and the packages are moved toward the circuit board so that the feet 617 and solder balls 716 rest on the solder or solder paste 625, 725.

(47) Thereafter, the solder or paste (or second-level interconnect solder balls) is heated to reflow the solder and complete the electrical connection. Typically, where solder or solder paste is provided, feet or balls are wetted by the reflowed solder, so that the solder flows over the surfaces of the bond sites 623, 723 and onto the lower surfaces of the feet and the balls, as indicated at 645 and 765 in FIG. 6B.

(48) Heating to reflow the solder or solder paste, typically by passing the assembly through a reflow oven, requires raising the temperature of the assembly according to a time/temperature schedule suitable for the particular solder.

(49) FIG. 7 shows examples of reflow heating schedules for a conventional solder (broken line) and for a lead-free SnAg solder. The lead-free solder has a higher melting point and reflows more slowly and, accordingly, the assembly must be brought to a higher temperature and held there for a longer time for the lead-free solder than for the conventional solder. Particularly, for a typical lead-free solder, the temperature is raised during a pre-heat phase from about 150° C. to about 180° C. over a period of about 60 to 120 seconds; and then during a reflow phase lasting over 30 seconds the temperature is raised more rapidly to a peak temperature approaching about 240° C., and is held there for a period of about 10 to 20 seconds or longer and then is allowed to fall; the temperature throughout the reflow phase exceeds about 220° C. And particularly, for a conventional solder, the temperature is raised during a pre-heat phase from about 140° C. to about 170° C. over a period of about 60 to 120 seconds; and then during a reflow phase lasting over 30 seconds the temperature is raised more rapidly to a peak temperature in approaching about 225° C., and is held there for a period of about 5 seconds or longer; the temperature throughout the reflow phase exceeds about 200° C. An industry specification for solder bonding qualification calls for an ability to withstand 260° C. for thirty seconds or more.

(50) FIG. 8 is a graph of the results of thermal cycling that establish a crystallization transition temperature (generally 800) where the resistance begins to fall on the heat up cycle, on the order of 250° or higher, including at least 260° for materials A-D. Also, the graph illustrates that the resistance in the crystalline phase increases slightly with an increase in germanium Ge concentration.

(51) The following a chart shows characteristics of materials A and C.

(52) TABLE-US-00002 Soldering R SET SET 260 C/ 10 Window Current Speed Endurance 90 s Years Material 100K/ 300 uA ~2  10K Pass 145 C A 500K us (5X) Material 100K/ 300 uA 800 100K Pass 140 C C 500K ns (5X)

(53) As seen, each of the materials A and C shows a resistance window for the set and reset states of about 100K ohms and 500K ohms, respectively, so that the resistance of the reset state is five times that of the set state. For testing involving a set current of 300 μA, the set speed for Material A is about 2 μs. For Material C the set speed is about 800 ns. The endurance according to testing for Material A is about 10K cycles, whereas for material C the endurance is about 100K cycles. Both materials pass three times the solder bonding criteria extended from the standard 260° at 30 seconds up to 260° at 90 seconds. Also, Material A demonstrates 10 years endurance at 145° C. Material C demonstrates 10 years endurance at 140° C.

(54) FIG. 9 is a graph showing test results for two samples of Material A, a failure rate versus baking time. FIG. 10 is a graph showing lifetime versus temperature (1/KBT) for the two samples. This testing demonstrates an activation energy Ea (as in Arrhenius equation) of about 2.7 electron volts for Material A, passing the endurance criterion of 145° C. for 10 years.

(55) FIG. 11 is a graph showing test results for two samples of Material C, a failure rate versus baking time. FIG. 12 is a graph showing lifetime versus temperature (1/KBT) for the two samples. This testing demonstrates an activation energy Ea of about 3.2 electron volts for Material A, passing the endurance criterion of 140° C. for 10 years. Material C however has a faster set speed at 800 ns, and can pass the solder bonding criteria.

(56) FIG. 13 illustrates the resistance distribution for a memory array comprising memory elements of Material A, in a memory at array having set and reset cells, and using three different set pulse magnitudes. The results plotted were based on tests after 10 set/reset cycles on the memory cells. The three different set pulse characteristics include 150 μA for 960 ns, 200 μA for 960 ns and 300 μA for 960 ns. The longer set pulses resulted in a tighter and lower resistance distribution. The reset pulse in this example was 400 μA for 40 ns. In the test, equal numbers of cells were exposed to each of the four conditions, including three set conditions and one reset condition.

(57) FIG. 14 illustrates the distribution measured after exposing the integrated circuit to a ramp to 260° C. for 90 seconds to verify the solder bonding criterion. As seen, the integrated circuit passes the criterion in which the resistance in the reset condition remains above 500 K ohms and in the set condition remains below 100 K ohms for the set pulse amplitudes of 200 and 300 μA.

(58) FIG. 15 illustrates the resistance distribution for a memory array comprising memory elements of Material C, in a memory at array having set and reset cells, and using three different set pulse magnitudes. The results plotted were based on tests after 10 set/reset cycles on the memory cells. The three different set pulse characteristics include 300 μA for 800 ns, 300 μA for 960 ns and 200 μA for 960 ns. The longer set pulses at higher magnitude resulted in a tighter and lower resistance distribution. The reset pulse in this example was 400 μA for 40 ns. In the test, equal numbers of cells were exposed to each of the four conditions, including three set conditions and one reset condition.

(59) FIG. 16 illustrates the distribution measured after exposing the integrated circuit to a ramp up to 260° C. for 90 seconds, to verify solder bonding criterion. As seen, both of the 300 μs set pulses can pass the solder bonding criterion, with less than 0.5% yield loss for the 90 second exposure, where the passing criterion requires the resistance in the reset condition remains above 500 K ohms and in the set condition remains below 100 K ohms.

(60) Other testing of materials A-D shows that at least materials A and C in this new class of materials, can be set with pulse lengths substantially less than 1000 ns.

(61) Testing of the examples of materials in the new class of SiO.sub.x doped, Ge-rich Ge.sub.xSb.sub.yTe.sub.z material used for phase change memory demonstrates that the Ge, Sb, Te, Si and O elements can be used in combinations effective to have a set speed less than 1000 ns, and as low as 640 ns. Also, this testing demonstrates that within this new class of phase change materials, the Ge, Sb, Te, Si and O elements can be used in combinations effective to have crystallization transition temperatures greater than 250° C. Also, this testing demonstrates that for memory arrays on integrated circuits using this new class of phase change materials, the Ge, Sb, Te, Si and O elements can be used in combinations effective to pass solder bonding criterion.

(62) FIG. 17 is a simplified block diagram of an integrated circuit 1800 including an embedded phase change memory array 1802 of memory cells having memory elements formed by SiO.sub.x doped, Ge-rich Ge.sub.xSb.sub.yTe.sub.z materials as described herein. A row/level line decoder 1804 having read, set and reset modes is coupled to, and in electrical communication with, a plurality of word lines 1806 arranged in levels and along rows in the array 1802. A column/level decoder 1808 is in electrical communication with a plurality of bit lines 1810 arranged in levels and along columns in the array 1802 for reading, setting, and resetting the memory cells in the array 1802. Addresses are supplied on bus 1812 to row/level decoder 1804 and column/level decoder 1808. Sense circuitry (Sense amplifiers) and data-in structures in block 1814, including voltage and/or current sources for the read, set, and reset modes are coupled to column/level decoder 1808 via data bus 1816. Data is supplied via a data-in line 1818 from input/output ports on integrated circuit 1800, or from other data sources internal or external to integrated circuit 1800, to data-in structures in block 1814.

(63) Other circuitry 1820 may be included on integrated circuit 1800, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array 1802, in which case the array is used as embedded memory accessed by intra-chip connections. Data is supplied via a data-out line 1822 from the sense amplifiers in block 1814 to input/output ports on integrated circuit 1800, or to other data destinations internal or external to integrated circuit 1800 usable for inter-chip communications.

(64) A controller 1824 implemented in this example, using a bias arrangement state machine, controls the application of bias circuitry voltage sources and current sources 1826 for the application of bias arrangements, including fast read, set, reset and verify voltages, and/or currents for the word lines and bit lines. The controller includes control circuitry configured for switching layers having a threshold voltage depending on the structure and composition of the memory cells, by applying a voltage to a selected memory cell so that the voltage on the switch in the select memory cell is above the threshold, and a voltage to an unselected memory cell so that the voltage on the switch in the unselected memory cell is below the threshold during a read operation or other operation accessing the selected memory cell.

(65) Controller 1824 may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller 1824 comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller 1824.

(66) In operation, each of the memory cells in the array 1802 stores data depending upon the resistance of the corresponding memory element. The data value may be determined, for example, by comparison of current on a bit line for a selected memory cell to that of a suitable reference current by sense amplifiers of sense circuitry (block 1814). The reference current can be established so that a predetermined range of currents correspond to a logical “0”, and a differing range of current corresponds to a logical “1”. In some embodiments, multiple bits per cell can be stored.

(67) In some embodiments, the memory array 1802 is pre-coded with data, such as a computer program, prior to mounting the integrated circuit in a data processing system. This can be implemented using factory programming during the manufacturing process before or after packaging, and before delivery to customers.

(68) Reading or writing to a memory cell of array 1802, therefore, can be achieved by applying a suitable voltage to bit lines using a voltage source so that current flows through the selected memory cell.

(69) FIG. 18 illustrates a process flow diagram of a manufacturing process for manufacturing an integrated circuit with a pre-coded array of memory cells, the memory cells having memory elements comprising SiO.sub.x doped, Ge-rich Ge.sub.xSb.sub.yTe.sub.z materials as described herein.

(70) At step 1900, the first electrode 120 having a contact area 122 is formed, extending through dielectric 130. In the illustrated embodiment, the first electrode 120 comprises TiN and the dielectric 130 comprises SiN. In some embodiments, the contact area 122 of the first electrode 120 has a sub-lithographic width or diameter.

(71) The first electrode 120 and the dielectric 130 can be formed by a number of processes. For example, a layer of electrode material can be formed on the top surface of access circuitry (not shown), followed by patterning of a layer of photoresist on the electrode layer using standard photolithographic techniques so as to form a mask of photoresist overlying the location of the first electrode 120. Next, the mask of photoresist is trimmed using, for example, oxygen plasma to form a mask structure having sub-lithographic dimensions overlying the location of the first electrode 120. Then, the layer of electrode material is etched using the trimmed mask of photoresist, thereby forming the first electrode 120 having a sub-lithographic diameter. Next dielectric 130 is formed and planarized.

(72) At step 1910, a body of phase change material in the class of SiO.sub.x doped, Ge-rich Ge.sub.xSb.sub.yTe.sub.z materials described herein is deposited on the first electrode 120 and dielectric 130. The deposition of Ge-rich Ge.sub.xSb.sub.yTe.sub.z and silicon oxide may be carried out by co-sputtering of a Ge—Sb—Te target, and an SiO.sub.2 target in an argon atmosphere. Alternatively, the deposition of Ge-rich Ge.sub.xSb.sub.yTe.sub.z and silicon oxide can be carried out using sputtering with a single composite Ge.sub.xSb.sub.yTe.sub.z and Si target with an oxygen reactive process. Other processes may be used as suits a particular phase change material and memory cell structure.

(73) An optional annealing (not shown) can be performed to crystallize the phase change material. In the illustrated embodiment the thermal annealing step is carried out at 300° C. for 100 seconds in a nitrogen ambient. Alternatively, since subsequent back-end-of-line processes performed to complete the device may include high temperature cycles and/or a thermal annealing step depending upon the manufacturing techniques used to complete the device, in some embodiments the annealing may be accomplished by following processes, and no separate annealing step is added to the manufacturing line.

(74) Next, at step 1920 a second electrode 140 is formed, resulting in the structure illustrated in FIG. 1. In the illustrated embodiment, the second electrode 140 comprises TiN.

(75) Next, at step 1930 back-end-of-line (BEOL) processing is performed to complete the semiconductor process steps of the chip. The BEOL processes can be standard processes as known in the art, and the processes performed depend upon the configuration of the chip in which the memory cell is implemented. Generally, the structures formed by BEOL processes may include contacts, inter-layer dielectrics and various metal layers for interconnections on the chip including circuitry to couple the memory cell to peripheral circuitry. These BEOL processes may include deposition of dielectric material at elevated temperatures, such as depositing SiN at 400° C. or high density plasma HDP oxide deposition at temperatures of 500° C. or greater. As a result of these processes, control circuits and biasing circuits as shown in FIG. 17 are formed on the device including circuitry for set and reset operations.

(76) This process can be extended to 3D memory arrays, by forming multiple layers of memory array circuits.

(77) After BEOL processing, the chip be packaged in a single-chip or multichip package according to a particular need (1940). Also, the chip can be pre-coded with data such as without limitation, a computer program or control parameters (1950). The pre-coding can be performed before or after the packaging step 1940.

(78) The pre-coded chip can then be solder mounted on a patterned circuit substrate, such as a printed circuit board, without significant loss of the pre-coded data (1960). In this context significant loss of pre-coded data would involve loss of amounts of data that are not recoverable using error correction available on the integrated circuit, or would involve loss of amounts of data that interfere with functionality of the integrated circuit in its mission function.

(79) In FIG. 19, four one-transistor, one memory element (1T/1R) memory cells 2030, 2032, 2034, 2036 having memory elements 2040, 2042, 2044, 2046 which are body of SiO.sub.x doped, Ge-rich Ge.sub.xSb.sub.yTe.sub.z material phase change material, representing a small section of an array. Arrays of this type can be used on a memory device, and as embedded memory as discussed above.

(80) Sources of each of the access transistors of memory cells 2030, 2032, 2034, 2036 are connected in common to a first-type access line 2054 (i.e. source line) that terminates in a source line termination of circuit 2055, such as a ground terminal. In another embodiment, the source lines of the access devices are not shared between adjacent cells, but are independently controllable. The source line termination circuit 2055 may include bias circuitry such as voltage sources and current sources, and decoding circuits for applying bias arrangements, other than ground, to the access line 2054, in some embodiments.

(81) A plurality of second-type access lines, including word lines 2056, 2058, extend in parallel along a first direction. Word lines 2056, 2058 are in electrical communication with word line decoder 2014. The gates of access transistors of memory cells 2030 and 2034 are connected to word line 2056, and the gates of access transistors of memory cells 2032 and 2036 are connected in common to word line 2058.

(82) A plurality of third-type access lines including bit lines 2060, 2062 extend in parallel in a second direction and are in electrical communication with bit line decoder 2018, and sense amplifiers and data-in circuits 2024. In the illustrated embodiment, each of the memory elements are arranged between the drain of the corresponding access device and the corresponding bit line. Alternatively, the memory elements may be on the source side of the corresponding access device. Control circuitry and biasing circuits (see FIG. 8) are coupled to the array, and provide means for applying set and reset operations to the memory cells.

(83) Alternatively, the memory cells can be organized in a cross-point architecture. The first electrode can be the access lines, such as word lines and/or bit lines. In such architecture, the access devices, such as diodes or OTS switches are arranged between the memory elements and the access lines.

(84) A method for manufacturing a circuit including an integrated circuit phase change memory having a memory element of SiO.sub.x doped, Ge-rich Ge.sub.xSb.sub.yTe.sub.z material, comprising:

(85) pre-coding a data set in the integrated circuit phase change memory by inducing a lower resistance state in some cells in the memory, and a higher resistance state in some other cells in the memory; and

(86) after the coding, mounting the integrated circuit phase change memory on a substrate using a procedure that includes thermal cycling such as solder bonding that induces temperatures between 200° C. and 260° C.

(87) A new class of phase change memory materials as described are characterized by high data retention, and a capability to pass the solder bonding thermal budget. This new class of phase change material is usable for embedded memory, as well as memory arrays in high density large-scale memory integrated circuits.

(88) While the present technology is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the disclosure and the scope of the following claims.