Systems and methods are described for predicting potential failures in flash memory devices by probing for memory cells with marginal programming characteristics. A method includes receiving a write request. The method also includes applying a predetermined number of programming pulses to a plurality of memory cells within a block of a flash memory device. The method also includes applying a verify pulse to each respective one of the plurality of memory cells. The method also includes storing programming status of the plurality of memory cells into a set of latches. The method also includes determining, based on the stored programming status, a total number of memory cells within the block that fall outside of one or more predetermined expected ranges. The method also includes identifying the block as a block in risk when the total number of memory cells satisfies a predetermined risk threshold.

A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.

A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Provided is a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory unit including a plurality of memory blocks; a voltage supply circuit configured to generate a plurality of operating voltages and output the generated operating voltages to at least two global line groups during a program operation on the memory unit; a pass circuit configured to couple word lines of the memory blocks to the at least two global line groups; and a control logic configured to control the voltage supply circuit and the pass circuit such that during a program verify operation of the program operation, a program verify voltage is applied to a selected memory block of the memory blocks, and a set voltage is applied to a share memory block sharing with the selected memory block among unselected memory blocks.

Provided is a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory unit including a plurality of memory blocks; a voltage supply circuit configured to generate a plurality of operating voltages and output the generated operating voltages to at least two global line groups during a program operation on the memory unit; a pass circuit configured to couple word lines of the memory blocks to the at least two global line groups; and a control logic configured to control the voltage supply circuit and the pass circuit such that during a program verify operation of the program operation, a program verify voltage is applied to a selected memory block of the memory blocks, and a set voltage is applied to a share memory block sharing with the selected memory block among is unselected memory blocks.

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.