A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.

Systems, apparatuses, and methods provide for technology for distinguishing an erased state, a first pass programmed state, and a second pass programmed state of a memory page. A threshold voltage state verify sense is performed. A memory page status is determined based on the threshold voltage state verify sense. The memory page status is one of erased, programmed with first pass data, and programmed with second pass data based on the threshold voltage state verify sense. A program continuation is performed after a program interruption based on the memory page status.

A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.

A processing device in a memory system receives a request to execute a first operation of a first input/output (I/O) operation type at a memory device. The processing device further determines whether a second operation of a second I/O operation type is being executed at the memory device. Responsive to determining that the second operation is being executed, the processing device suspends the second operation after a delay time period, the delay time period corresponds to a first operation weight of the first operation and a second operation weight of the second operation, executes the first operation at the memory device, and responsive to determining that executing the first operation is complete, the processing device resumes execution of the second operation at the memory device.

A memory system, a memory controller and an operating method are disclosed. By inputting a read command to the memory device, starting to input data for a write command when the write command is input to the memory device while the memory device performs a read sensing operation for the read command, and inputting, to the memory device, data for the write command when input of the write command is started, it is possible to enhance the write performance of the memory system when the memory system executes a write operation after a read operation.

A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

According to one embodiment, a semiconductor memory device including a first memory cell; a word line; a bit line; a row decoder; a sense amplifier including a latch circuit; a data register; and a control circuit capable of suspending a write operation during the write operation of the first memory cell to perform a read operation of the first memory cell. In a read operation of the first memory cell performed while suspending the write operation, the row decoder applies a read voltage to the word line, and the sense amplifier transmits data read from the first memory cell to the data register as read data when writing to the first memory cell is completed, and transfers write data held by the latch circuit to the data register as the read data when the writing is not completed.

A memory controller and a storage device including the same are provided. The memory controller includes a memory channel controller configured to perform erase/program, read, and erase/program suspend operations for a flash memory, a flash translation layer configured to control an operation of the memory channel controller by receiving a write/read command, and transmit a completion for the write/read command, a host interface configured to receive the write/read command from a host, transmit the write/read command to the flash translation layer, receive the completion from the flash translation layer, and calculate a write/read latency for the write/read command based on the completion, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the calculated write/read latency, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

In one example, a nonvolatile memory device, such as a NAND flash memory device, includes an array of non-volatile memory cells. Program operations performed by the memory may be suspended (e.g., in order to service a high priority read request). The memory device includes a timer to track a duration of time the program operation is suspended. Upon program resume, the controller applies a program voltage after resume that is adjusted based on the duration of time the program operation is suspended.