Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

A memory system includes: a memory device including a memory cell array and a page buffer circuit, the memory device performing a data program operation or a data erase operation, suspending the data program operation or the data erase operation in response to a suspend command, performing a data read operation of storing read data from the memory cell array in the page buffer circuit in response to a read command, and performing a data output operation of outputting the read data stored in the page buffer circuit; and a memory controller outputting a pre-resume command to the memory device between a first time at which the data read operation is complete and a second time at which the data output operation starts.

A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Provided herein is a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may be configured to perform a plurality of program loops, each including a program pulse apply operation and a program verify operation, on selected memory cells of the plurality of memory cells. The control logic may be configured to control, in response to a suspend command, the peripheral circuit to suspend an n-th program loop of the plurality of program loops, where n is a natural number of 1 or more, and configured to control, in response to a resume command, the peripheral circuit to resume the suspended n-th program loop after performing a recovery pulse apply operation compensating for charges detrapped from a channel area of the selected memory cells.

A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a first operation, corresponding to a first command, on the memory cell array. The control logic is configured to control the first operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to suspend the performance of the first operation and perform a second operation corresponding to a second command, in response to the to second command being received while the first operation is being performed.

A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

There are provided a memory system and an operating method thereof. The memory system includes a semiconductor memory configured to perform a memory operation and perform a suspend operation of suspending a currently performed memory operation and a controller configured to control the memory operation. The controller controls the semiconductor memory to perform the suspend operation in a suspension-allowed period by determining a detailed operation period of the currently performed memory operation.

A processing device in a memory system receives a request to execute a first operation of a first input/output (I/O) operation type at a memory device. The processing device further determines whether a second operation of a second I/O operation type is being executed at the memory device. Responsive to determining that the second operation is being executed, the processing device suspends the second operation after a delay time period, the delay time period corresponds to a first operation weight of the first operation and a second operation weight of the second operation, executes the first operation at the memory device, and responsive to determining that executing the first operation is complete, the processing device resumes execution of the second operation at the memory device.

A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.