A sensor assembly with a sensing element sends a sensor signal from the sensing element to attached process transmitter over sensor connection wires. The sensor assembly has memory circuitry for storing information related to the sensor assembly and interface circuitry that provides for digital communication of the stored information with the attached process transmitter. This digital communication is sent over the sensor connection wires.

A sensor assembly with a sensing element sends a sensor signal from the sensing element to attached process transmitter over sensor connection wires. The sensor assembly has memory circuitry for storing information related to the sensor assembly and interface circuitry that provides for digital communication of the stored information with the attached process transmitter. This digital communication is sent over the sensor connection wires.

A parameter determining apparatus for estimating temperature of a switching element of an inverter is disclosed. The parameter determining apparatus of the present disclosure includes an inverter unit including a power semiconductor module configured with at least one or more switching elements, and a control unit configured to determine an initial collector-emitter voltage of each of the switching elements and collector-emitter resistance of each thereof by linearizing a collector-emitter voltage of each of the switching elements at a certain temperature.

A parameter determining apparatus for estimating temperature of a switching element of an inverter is disclosed. The parameter determining apparatus of the present disclosure includes an inverter unit including a power semiconductor module configured with at least one or more switching elements, and a control unit configured to determine an initial collector-emitter voltage of each of the switching elements and collector-emitter resistance of each thereof by linearizing a collector-emitter voltage of each of the switching elements at a certain temperature.

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

A RTD measurement device comprises a current splitter connected to a single current source. The current splitter splits the current from the current source into two currents and continuously monitors the two currents and adjusts them to be the same value.

A circuit arrangement comprises a first branch comprising a resistor of variable resistance and a diode-connected bipolar transistor and a second branch comprising a resistor of fixed resistance and another diode-connected bipolar transistor. A control loop reproduces a voltage drop at the resistor of variable resistance to a voltage drop at the resistor of fixed resistance. Output terminals are connected to the bipolar transistors to supply a differential voltage. The circuit arrangement may be used as an analog frontend circuit in a gas sensor or a temperature sensor arrangement.

A circuit arrangement comprises a first branch comprising a resistor of variable resistance and a diode-connected bipolar transistor and a second branch comprising a resistor of fixed resistance and another diode-connected bipolar transistor. A control loop reproduces a voltage drop at the resistor of variable resistance to a voltage drop at the resistor of fixed resistance. Output terminals are connected to the bipolar transistors to supply a differential voltage. The circuit arrangement may be used as an analog frontend circuit in a gas sensor or a temperature sensor arrangement.

A wiring board includes an insulating substrate composed of a stack of a plurality of insulating layers, the insulating substrate having an upper face, a lower face, and side faces; and a plurality of line conductors formed of platinum or a metallic material comprising platinum as a main component, the plurality of line conductors each including a first end and a second end located on a side opposite to the first end, the plurality of line conductors being respectively disposed in interlayers between the plurality of insulating layers, in the line conductors, a line width of a line conductor located in an interlayer among the interlayers which interlayer is closest to the upper face or the lower face of the insulating substrate being greater than a line width of a line conductor located in each of the other interlayers.