An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.

The disclosure provides an apparatus for aligning first and second plates that are parallel to each other and have the same orientation. The apparatus includes a detector that detects composite small-angle X-ray scattering emitted from patterns of the first and second plates that are perpendicularly impinged by X-ray, and a moving unit that aligns the first and second plates according to a composite amplitude distribution of the composite small-angle X-ray scattering. Therefore, the first and second plates are aligned to each other accurately.

An object of the disclosure is to provide a pattern inspection and measurement apparatus that can accurately specify a corner point formed on a sample. The pattern inspection and measurement apparatus according to the disclosure specifies a pair of corner points as a corner pair candidate on design data, and specifies a corner point on an actually formed shape pattern in accordance with a relative relation between the corner pair candidate on the design data and the corner pair candidate in the shape pattern (see FIG. 13).

Methods for locating and characterizing defects can include performing a first scan of a substrate to produce a first defect map including a first set of coordinates of one or more defects of the substrate and performing a second scan of one or more regions of the substrate associated with the defects based on the first defect map to produce one or more electron channeling contrast (ECC) images of the defects. Characterization of the defects can be based on the ECC images alone or in combination with other techniques. Such methods can include determining a second set of coordinates associated with the one or more defects based on the ECC images and directing an ion beam toward the substrate and milling the substrate based on the second set of coordinates.

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

A method for raising a polishing pad for polishing a silicon wafer, wherein a polishing pad made of foamed urethane resin is attached to a polishing machine, after dressing is performed, dummy polishing is performed, after processing to remove the polishing residues that have built up in the polishing pad by the dummy polishing is then performed, an amount of polishing residues in the polishing pad is measured, and a rise of the polishing pad subjected to the dummy polishing is judged based on the measured amount of polishing residues. As a result, a method for raising a polishing pad can improve the particle level in the polishing pad life early stage.

A multi-layer arrangement of III-V semiconductor layers includes a strained III-V semiconductor layer having a concentration of a constituent element which effects intensity of a conductive channel formed in the multi-layer arrangement. Lattice parameters of the strained III-V semiconductor layer are determined by generating a first scan in a Qx direction for a chosen reflection in reciprocal space based on diffracted X-Ray beam intensity measurements in the Qx direction. A second scan is generated in a Qz direction for the chosen reflection in the reciprocal space based on diffracted X-Ray beam intensity measurements in the Qz direction. The second scan is aligned with a diffracted X-Ray peak in the first scan which identifies the strained III-V semiconductor layer. The degree of strain of the strained III-V semiconductor layer is determined based on the first scan and the concentration of the constituent element based on the second scan.

An electron source emits an electron beam. The electron beam is received by a beam limiting assembly. The beam limiting assembly has a first beam limiting aperture with a first diameter and a second beam limiting aperture with a second diameter larger than the first diameter. The first beam limiting aperture receives the electron beam. This beam limiting assembly reduces the influence of Coulomb interactions.

A defect inspection device is provided with an illumination optical system that irradiates light or an electron beam onto a sample, a detector that detects a signal obtained from the sample through the irradiation of the light or electron beam, a defect detection unit that detects a defect candidate on the sample through the comparison of a signal output by the detector and a prescribed threshold, and a display unit that displays a setting screen for setting the threshold. The setting screen is a two-dimensional distribution map that represents the distribution of the defect candidates in a three dimensional feature space having three features as the axes thereof and includes the axes of the three features and the threshold, which is represented in one dimension.

A detector includes a set of sensing elements, first section circuitry communicatively coupling a first set of sensing elements to an input of first signal processing circuitry, second section circuitry communicatively coupling a second set of sensing elements to an input of second signal processing circuitry, and interconnection circuitry communicatively coupling an output of the first signal processing circuitry to an output of the second signal processing circuitry. The interconnection circuitry may include an interconnection layer having interconnection switching elements communicatively coupled to outputs of analog signal paths of the detector. Interconnection switching elements may communicatively couple the outputs of adjacent analog signal paths. The detector may also include signal processing circuitry that includes a plurality of converters. The interconnection circuitry may be configured to selectively couple outputs of the first and second signal processing circuitry to the converters.