Patent classifications
G01N2223/6116
Method for evaluating semiconductor substrate
The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.
Automatic defect detection and classification for high throughput electron channeling contrast imaging
Imaging and processing techniques are employed to identify crystalline defects obtained by ECCI from surrounding topography and is combined with defect counting and automatic classification.
X-RAY THIN FILM INSPECTION DEVICE
An X-ray thin film inspection device of the present invention includes an X-ray irradiation unit 40 installed on a first rotation arm 32, an X-ray detector 50 installed on a second rotation arm 33, and a fluorescence X-ray detector 60 for detecting fluorescence X-rays generated from an inspection target upon irradiation of X-rays. The X-ray irradiation unit 40 includes an X-ray optical element 43 comprising a confocal mirror for receiving X-rays radiated from an X-ray tube 42, reflects plural focused X-ray beams monochromatized at a specific wavelength and focuses the plural focused X-ray beams to a preset focal point, and a slit mechanism 46 for passing therethrough any number of focused X-ray beams out of the plural focused X-ray beams reflected from the X-ray optical element 43.
SEMICONDUCTOR WAFER AND METHOD OF INSPECTING SEMICONDUCTOR WAFER
Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).
SHAPED APERTURE SET FOR MULTI-BEAM ARRAY CONFIGURATIONS
An aperture array for a multi-beam array system and a method of selecting a subset of a beam from a multi-beam array system are provided. The aperture array comprises an array body arranged proximate to a beam source. The array body comprises a plurality of apertures, at least two of the apertures having different geometries. The array body is movable, via an actuator, relative to an optical axis of the beam source, such that a subset of a beam from the beam source is selected based on the geometry of the aperture that is intersected by the optical axis.
AUTOMATIC DESKEW USING DESIGN FILES OR INSPECTION IMAGES
Deskew for image review, such as SEM review, aligns inspection and review coordinate systems. Deskew can be automated using design files or inspection images. A controller that communicates with a review tool can align a file of the wafer, such as a design file or an inspection image, to an image of the wafer from the review tool; compare alignment sites of the file to alignment sites of the image from the review tool; and generate a deskew transform of coordinates of the alignment sites of the file and coordinates of alignment sites of the image from the review tool. The image of the wafer may not contain defects.
Full Beam Metrology For X-Ray Scatterometry Systems
Methods and systems for characterizing dimensions and material properties of semiconductor devices by full beam x-ray scatterometry are described herein. A full beam x-ray scatterometry measurement involves illuminating a sample with an X-ray beam and detecting the intensities of the resulting zero diffraction order and higher diffraction orders simultaneously for one or more angles of incidence relative to the sample. The simultaneous measurement of the direct beam and the scattered orders enables high throughput measurements with improved accuracy. The full beam x-ray scatterometry system includes one or more photon counting detectors with high dynamic range and thick, highly absorptive crystal substrates that absorb the direct beam with minimal parasitic backscattering. In other aspects, model based measurements are performed based on the zero diffraction order beam, and measurement performance of the full beam x-ray scatterometry system is estimated and controlled based on properties of the measured zero order beam.
Using multiple sources/detectors for high-throughput X-ray topography measurement
An apparatus for X-ray topography includes a source assembly, a detector assembly, a scanning assembly and a processor. The source assembly is configured to direct multiple X-ray beams so as to irradiate multiple respective regions on a sample, wherein the regions partially overlap one another along a first axis of the sample and are offset relative to one another along a second axis of the sample that is orthogonal to the first axis. The detector assembly is configured to detect the X-ray beams diffracted from the sample and to produce respective electrical signals in response to the detected X-ray beams. The scanning assembly is configured to move the sample relative to the source assembly and the detector assembly along the second axis. The processor is configured to identify defects in the sample by processing the electrical signals, which are produced by the detector assembly while the sample is moved.
CRYSTAL DEFECT OBSERVATION METHOD FOR COMPOUND SEMICONDUCTOR
A sample (4) is created by cutting out a device on a plane (10-10). The device has a gate electrode (3) formed along a direction [2-1-10] on a plane c (0001) of a compound semiconductor (1) having a wurtzite structure. Edge dislocations having Burgers vectors of 1/3[2-1-10] and 1/3[−2110] and mixed dislocations having Burgers vectors of 1/3[2-1-13] and 1/3[−2113] are observed by making an electron beam (5) incident on the sample (4) from a direction [−1010] using a transmission electron microscope.
ELECTRON BEAM INSPECTION APPARATUS AND ELECTRON BEAM INSPECTION METHOD
An electron beam inspection apparatus according to one aspect of the present invention includes an image acquisition mechanism to acquire a secondary electron image by scanning a substrate, on which a figure pattern is formed, with an electron beam, and detecting a secondary electron emitted due to irradiation with the electron beam by the scanning, a resize processing unit to perform, using design pattern data being a basis of the figure pattern, resize processing on the figure pattern to enlarge its size in a scan direction of the electron beam, a first developed image generation unit to generate, using the design pattern data which has not been resized, a first developed image by developing an image of a design pattern of a region corresponding to the secondary electron image, a second developed image generation unit to generate, using partial patterns enlarged by the resize processing in the figure pattern having been resized, a second developed image by developing an image of partial patterns in a region corresponding to the secondary electron image, a map generation unit to generate a pseudo defect candidate pixel map which can identify a pseudo defect candidate pixel that has no pattern in the first developed image and has a pattern in the second developed image, a reference image generation unit to generate a reference image of the region corresponding to the second electron image, and a comparison unit to compare, using the pseudo defect candidate pixel map, the second electron image with the reference image of the region corresponding to the second electron image.