A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.

A method for testing a device under test (DUT) is disclosed. The method comprises communicating signals wirelessly from a first plurality of patch antennae disposed on a top surface of the DUT to a second plurality of patch antennae disposed on a printed circuited within a handler device, wherein the handler device is operable to place the DUT in a socket of a tester system, and wherein the tester system comprises the handler device and a test fixture. The method further comprises communicating the signals captured by the second plurality of patch antennae using microstrip transmission lines to a patch antenna on the printed circuit board, wherein a first waveguide is mounted to the patch antenna using a first waveguide flange, and wherein the first waveguide flange is coupled to a first end of the first waveguide.

A testing apparatus for testing a circuit board is disclosed, which includes an upper plate, a lower plate, and an adaptor circuit board. A plurality of positioning units is received in the lower plate. Each positioning unit has a plurality of length-variable test probes secured therein. Each test probe has a shell and upper and lower probe ends at opposite ends of the shell. In test, the circuit board is put on the lower plate and the upper plate is lowered to push the circuit board and the lower plate toward the adaptor circuit board. The upper ends of the test probes engage with electrical connectors of the circuit board and the lower ends thereof engage with the adaptor circuit board whereby test of the circuit board can be automatically performed by the testing apparatus.

The present disclosure provides a test device and a test method using the test device. The test device includes a first fastener structure for fastening a to-be-tested substrate with first touch lines, a second fastener structure for fastening a test match panel with second touch lines, and the first touch lines and the second touch lines forming a touch module, a third fastener structure for supporting a change-over flexible printed circuit board, a signal input structure for electrically connecting to one of a circuit board in the test match panel and the first touch lines through the change-over flexible printed circuit board, and inputting trigger data signals, a sensing signal capture structure for capturing touch sensing signals in the first touch line or the second touch lines.

A differential pin to RF adaptor includes a center conductor contact with an RF connector on one end and a signal contact on the other end. An insulating sleeve surrounds the central contact. A reference contact surrounds the insulating sleeve. The signal pin of the differential pair interfaces with the center conductor contact of the RF connector. The adaptor is structured to slide down over a pair of pins/leads so that the reference contact abuts a circuit board attached to the pins. The pins/leads are shielded all the way to the circuit board, which shields/isolates the pins from common mode and other types of interference. The adaptor maintains the shape of the signal pin and the reference pin during testing. The adaptor maintains a fixed impedance of the pins, which reduces or eliminates uncontrolled impedance and hence preserves system frequency response and reduces/eliminates erroneous ripple currents.

Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation.

A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.

The present disclosure provides a testing fixture for holding a device under test (DUT). The testing fixture includes a base, a frame, a recessed portion, a plurality of sets of electrical contacts and a plurality of electrical lines. The frame extends upward along an outer perimeter of an upper surface of the base. The recessed portion is surrounded by the frame and the upper surface of the base, and the DUT is received in the recessed portion. The plurality of sets of electrical contacts are disposed on the recessed portion and arranged in a rotationally symmetrical manner, wherein a plurality of plated through holes of the DUT are in contact with one set of the electrical contacts after the DUT is assembled with the testing fixture.

A wafer probe station system for reliability testing of a semiconductor wafer. The wafer probe station is capable of interfacing with interchangeable modules for testing of semiconductor wafers. The wafer probe station can be used with different interchangeable modules for wafer testing. Modules, such as probe card positioners and air-cooled rail systems, for example, can be mounted or docked to the probe station. The wafer probe station is also provided with a front loading mechanism having a rotatable arm that rotates at least partially out of the probe station chamber for wafer loading.

A wafer testing system and a method of testing a wafer include placing a wafer on a vacuum chuck containing a plurality of vacuum zones, determining a warpage of the wafer, providing a different magnitude of vacuum suction to different vacuum zones at the same time based on the determined warpage of the wafer to reduce the warpage of the wafer, and testing the wafer.