Disclosed are methods and circuits to measure independently of duty cycles a pulsed current of a pass transistor of a switched circuit. Methods and circuits of one embodiment may be applied to precisely operate DC-to-DC converters such as buck converters in the most efficient operation modes. Another embodiment can be used to measure the pulsed current independently of duty cycle over a wide range of current values.

A circuit for comparing a voltage with a threshold, including: first and second nodes of application of the voltage; a first branch including a first transistor series-connected with a first resistor between first and second nodes; a second branch parallel to the first branch, including second and third series-connected resistors forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being connected to a control node of the first transistor; and a third branch including a second transistor in series with a resistive and/or capacitive element, between the control node of the first transistor and the first or second node, a control node of the second transistor being connected to the junction point of the first transistor and of the first resistor.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

According to one embodiment, a current detecting circuit includes: a normally-ON type first switching element that includes a drain, a source, and a gate; a normally-OFF type second switching element including a drain that is connected to the source of the first switching element, a source that is connected to the gate of the first switching element, and a gate; and a differential amplification circuit that outputs a voltage according to a voltage between the drain and the source of the second switching element.

A zero current detection system for a switching regulator is provided. The switching includes an inductor. In the zero current detection system, a comparator has a positive input coupled to a terminal of the inductor and an output terminal for outputting a comparison result signal; a first signal latch circuit has a clock terminal for receiving the comparison result signal and outputting a latched output signal; a delay line module starts counting upon receipt of the latched output signal, and then outputs a zero current detection signal after counting a delay time; in response to the zero current detection signal, a voltage sampling module samples a node voltage at two different time points, to generate two sampling voltages; a delay control module adjusts the delay time of the delay line module according to the two sampling voltages.

False detection relating to overcurrent is prevented, and it is determined with no dead time whether or not the current of a main element is an overcurrent. By a gate signal indicating conductivity being applied to the gate of a sense element earlier than to a main element when the main element is caused to be conductive, and overshoot caused by a differential circuit of the sense element gate input portion being caused before current flows into the main element, it is possible to prevent false detection relating to overcurrent, and determine with no dead time whether or not the current of the main element is an overcurrent.

An apparatus, method and integrated circuit for broad-range current measurement using variable resistance are disclosed. Embodiments of an apparatus for sensing current through a transistor device may include an interface configured to receive a current from the transistor device for sensing. In an embodiment, the apparatus may also include a sensor component coupled to the interface and configured to receive the current from the transistor device and to generate a responsive sensor voltage, the sensor component comprising an adjustable resistance component, a resistance value of the adjustable resistance component being selectable in response to a level of the current received at the interface.

To provide a current detection circuit capable of detecting with low current consumption that a prescribed current flows into a current measuring resistor. A current detection circuit is equipped with a reference voltage circuit which has two NMOS transistors having different threshold voltages and a resistor, and generates a reference voltage at the resistor, and a comparison output circuit which is comprised of a PMOS transistor, an NMOS transistor, and a measuring resistor connected in series in a manner similar to a PMOS transistor, an NMOS transistor, and a resistor and outputs a comparison result.

An autoranging ammeter with fast dynamic response allows improved dynamic measurement of rapidly changing direct electrical currents. The ammeter utilizes a low-cost dual threshold comparator mechanism coupled with an analog-to-digital converter and digital processing to rapidly select the appropriate current shunt resistor.

A current sensing circuit includes a current detection unit having a first resistance element; a first MOS-transistor and a first constant current source connected between a first output end of the current detection unit and a ground terminal; a second MOS-transistor and a second constant current source connected between a second output end of the current detection unit and the ground terminal; a third MOS-transistor having a source connected to the first output end and a gate connected to a drain of the second MOS-transistor; a second resistance element connected between an output terminal and the ground terminal; and a high withstand-voltage MOS-transistor connected between the third MOS-transistor and the output terminal to receive a predetermined control voltage, wherein the gates of the first and second MOS-transistors are commonly connected, and the gate of the first MOS-transistor is connected to the drain thereof.