Example capacitive-sensing rotary encoders and methods are disclosed herein. An example apparatus includes a rotary encoder structured to be mounted to a motor, the rotary encoder including a plurality of circumferential capacitive sensor arrays, each of the plurality of capacitive sensor arrays having an output representing a binary bit of a rotary encoder output, the rotary encoder output changing as a conductor rotates responsive to a rotatable shaft of the motor relative to the rotary encoder.

A measuring device is provided. The measuring device includes a base substrate, sensor electrodes, a temperature sensor, a high frequency oscillator, C/V conversion circuits for generating voltage signals corresponding to electrostatic capacitances of the sensor electrodes, an A/D converter for converting the voltage signals to digital values, a calculation unit for calculating measurement values indicating the electrostatic capacitances based on the digital values, and phase control circuits connected between the sensor electrodes and the high-frequency oscillator. Each of the conversion circuits includes an operational amplifier, and the high-frequency oscillator is connected to a non-inverting input terminal of the amplifier and is connected to an inverting input terminal thereof through a corresponding phase control circuit. The calculation unit stores parameters for setting admittances of the phase control circuits in association with temperatures and adjusts the admittances of the phase control circuits using a parameter associated with a detected temperature.

In an embodiment, a method for testing a functional integrity of a transistor component, the method includes causing a first change of a charge state of an internal capacitance between control terminals of the transistor component; determining a capacitance value of the internal capacitance based on the first change of the charge state; causing a second change of the charge state of the internal capacitance; and evaluating a resistance value of an internal resistance between the control terminals based on the determined capacitance value and the second change of the charge state.

Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2.sup.N amplifiers where N is a positive integer. By the capacitive sensor chip based on the power-aware dynamic charge-domain amplifier array, utilization efficiency of charges can be effectively improved, power consumption overheads nay be effectively saved, energy efficiency of a system is greatly improved and a driving capability of the subsequent-stage amplifier may be adaptively distributed according to the size of an input capacitance.

A capacitive sensor has a structure in which first transparent electrode portions and second transparent electrode portions formed from crystalline indium tin oxide (ITO) are provided on a base material by patterning. A bridge wiring portion formed from amorphous indium zinc oxide (IZO) is provided on each two adjacent first transparent electrode portions and a link continuous to them, with an insulating layer intervening between the bridge wiring portion and the two first transparent electrode portions and link. These two adjacent second transparent electrode portions are electrically connected together by the bridge wiring portion. The thickness of the second transparent electrode portion TE and the thickness of the bridge wiring portion TB satisfy the following expressions: 0.28×TE+83 nm≤TB≤0.69×TE+105 nm; and 30 nm≤TE≤50 nm.

An earth fault detection apparatus includes a switch group configured to switch between a first measurement path including a battery and a capacitor, and a second and third measurement paths including the battery, a positive/negative-side insulation resistance, and the capacitor; a reference resistance and a test switch; and a control unit calculating a first reference value based on each charging voltage in a case where the test switch is opened and the capacitor is charged, and calculating the insulation resistance with reference to a conversion map created to correspond to an electrostatic capacitance between a power supply line and ground, wherein the control unit calculates a second reference value based on each charging voltage in a case where the test switch is closed and the capacitor is charged for a shorter time, and estimates the electrostatic capacitance with reference to a predetermined test conversion map.

An earth fault detection apparatus includes a switch group configured to switch between a first measurement path including a battery and a capacitor, a second measurement path including the battery, a negative-side insulation resistance, and the capacitor, a third measurement path including the battery, a positive-side insulation resistance, and the capacitor; and a control unit configured to calculate a reference value, based on each charging voltage of the capacitor in each measurement path, and configured to calculate an insulation resistance with reference to a predetermined conversion map, in which the conversion map includes a conversion map corresponding to a capacitance of the capacitor, and the control unit estimates the capacitance of the capacitor, and refers to the conversion map corresponding to the capacitance of the capacitor that has been estimated.

Provided is a method for designing a battery module including a cell assembly in which a plurality of battery cells are stacked and a module case having an internal space in which the cell assembly is accommodated, the method including: a) setting a lowermost portion of the module case with respect to a direction of gravity as a design side, and setting a region between the design side and the cell assembly as a design space; and b) obtaining a relative permittivity ε.sub.r of the design space satisfying Equation 1 ε.sub.rε.sub.0A.sub.0/T.sub.1≤PCy by assuming that a shape of the design space is a form of a film having an area of A.sub.0 and a thickness of T.sub.0.

A multi-stage process for the production of an ISO 8217 Table 2 residual marine fuel Product Heavy Marine Fuel Oil from a Feedstock Heavy Marine Fuel Oil that is ISO 8217:2017 Table 2 compliant except for the Environmental Contaminants involves a Reaction System composed of one or more reactor vessels selected from a group reactor wherein said one or more reactor vessels contains one or more reaction sections configured to promote the transformation of the Feedstock Heavy Marine Fuel Oil to the Product Heavy Marine Fuel Oil. The Product Heavy Marine Fuel Oil has an Environmental Contaminant level less than 0.5 wt % and preferably a maximum sulfur content (ISO 14596 or ISO 8754) between the range of 0.05 mass % to 0.5 mass %. A process plant for conducting the process for conducting the process is also disclosed.

The invention relates to a device and a method for monitoring a DC link capacitor (C.sub.ZK) in an electrical DC link of a circuit (1) operated on a mains voltage V.sub.ac, the circuit comprising a power factor correction filter (PFC) and an inverter (20), the DC link capacitor (C.sub.ZK) to be monitored being between the power factor correction filter (PFC) and the inverter (20). During the operation of the circuit (1), the DC link capacitance C of the DC link capacitor (C.sub.ZK) is determined at least at certain time intervals over the operating time by measuring a power ripple W of a DC link voltage V.sub.ZK, which DC link voltage arises at the DC link capacitor (C.sub.ZK), said power ripple pulsing at twice the frequency of the mains voltage, and the remaining service life or the service life end and/or usability end of the DC link capacitor (C.sub.ZK) is determined, by means of an evaluation circuit (30), from the DC link capacitance C determined in this way.