In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

A duty cycle measuring circuit, the circuit comprising a synchronizer and a measurer, the synchronizer arranged such that when a signal to be measured comprising pulses having a pulse width and a pulse period is input to the synchronizer, synchronizing signals corresponding to each of pulse rising edge, pulse falling edge, pulse period start and pulse period end are output from the synchronizer, each synchronizing signal comprising a rising or falling edge, wherein the synchronizing signal outputs from the synchronizer are input to the measurer, and wherein the measurer is arranged to provide two measurement outputs based on the synchronizing signal inputs from the synchronizer, the measurement outputs comprising a first measurement output signal indicative of a pulse period measurement of the signal to be measured and a second measurement output signal indicative of a pulse width measurement of the signal to be measured.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

A receiving circuit, a transmission circuit and a system capable of reducing the effect of noise are provided. The receiving circuit includes: a pulse width detection unit which determines whether or not the pulse width of a pulse signal outputted based on comparison between a received-signal voltage and a reference voltage is smaller than a predetermined width; a reference voltage setting unit which, when the pulse width is smaller than the predetermined width, sets the reference voltage to be equal to or higher than a predetermined voltage; and an output control unit which, when the pulse width is equal to or larger than the predetermined width, causes a digital signal based on the pulse signal to be outputted or, when the pulse width is smaller than the predetermined width, performs control not to output the digital signal.

A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.

A duty cycle measuring circuit, the circuit comprising a synchronizer and a measurer, the synchronizer arranged such that when a signal to be measured comprising pulses having a pulse width and a pulse period is input to the synchronizer, synchronizing signals corresponding to each of pulse rising edge, pulse falling edge, pulse period start and pulse period end are output from the synchronizer, each synchronizing signal comprising a rising or falling edge, wherein the synchronizing signal outputs from the synchronizer are input to the measurer, and wherein the measurer is arranged to provide two measurement outputs based on the synchronizing signal inputs from the synchronizer, the measurement outputs comprising a first measurement output signal indicative of a pulse period measurement of the signal to be measured and a second measurement output signal indicative of a pulse width measurement of the signal to be measured.

In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.

A control method of multi-phase converters, wherein the multi-phase converter includes a plurality of switching circuits coupled in parallel between an input voltage and a load. The control method includes: comparing a feedback signal with a reference signal to generate a comparison signal, wherein the feedback signal is indicative of an output voltage provided to the load; determining the number of switching circuits for power operation based on the load current; detecting a period of the comparison signal; comparing the detected period of the comparison signal with a time threshold to determine whether a transient rise of load current has occurred; and getting all the switching circuits into power operation if a transient rise of load current is detected.

An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.