Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

A method is provided for testing switch signals of an inverter of an electric machine of a drive system of a motor vehicle. The electric machine is controlled via a pulse-width modulation generated by a control unit using a target duty cycle and a triangular-waveform voltage sequence. An actual duty cycle of a current pulse-width modulation is continuously ascertained from the switch signals and compared with the target duty cycle of the control unit.

A device for the detection of an ultra wide band signal, including a signal reception circuit, a signal divider circuit to divide the received signal into several frequency sub-bands, a circuit to determine the amplitude and duration of the received signal in each frequency sub-band, a circuit to compare the amplitude of the signal received in each frequency sub-band with an amplitude threshold, a circuit to compare the duration of the signal received in each frequency sub-band with a time threshold, and a decision circuit that determines that the received signal is of the ultra wide band type if the amplitude of the signal received in each frequency sub-band is higher than the amplitude threshold and if the duration of the signal received in each frequency sub-band is less than the time threshold.

Radio-frequency (RF) signal analysis includes slow-time signal processing and fast-time signal processing. Incoming RF pulses are captured according to a resource scheduling configuration. The fast-time signal processing is to prioritize the captured RF pulses for slow-time signal processing based on dynamic pulse-grading criteria. The slow-time signal processing is to perform relevance evaluation of the prioritized RF pulses, and to adjust the dynamic pulse-grading criteria and the resource scheduling configuration based on the relevance evaluation.

A control method of multi-phase converters, wherein the multi-phase converter includes a plurality of switching circuits coupled in parallel between an input voltage and a load. The control method includes: comparing a feedback signal with a reference signal to generate a comparison signal, wherein the feedback signal is indicative of an output voltage provided to the load; determining the number of switching circuits for power operation based on the load current; detecting a period of the comparison signal; comparing the detected period of the comparison signal with a time threshold to determine whether a transient rise of load current has occurred; and getting all the switching circuits into power operation if a transient rise of load current is detected.

A receiving circuit, a transmission circuit and a system capable of reducing the effect of noise are provided. The receiving circuit includes: a pulse width detection unit which determines whether or not the pulse width of a pulse signal outputted based on comparison between a received-signal voltage and a reference voltage is smaller than a predetermined width; a reference voltage setting unit which, when the pulse width is smaller than the predetermined width, sets the reference voltage to be equal to or higher than a predetermined voltage; and an output control unit which, when the pulse width is equal to or larger than the predetermined width, causes a digital signal based on the pulse signal to be outputted or, when the pulse width is smaller than the predetermined width, performs control not to output the digital signal.

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

One embodiment is a method of deconvolving overlapping first and second pulses in a photon-counting CT scanning system, the method comprising detecting a first pulse event having a first detected level; detecting a second pulse event having a second detected level; determining an amount of time that elapses between the detected first pulse event and the detected second pulse event; and reconstructing the first pulse and the second pulse using the first and second detected levels, the duration of time between the first and second pulse events, and a known pulse shape.

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.