An active digital electronic tuner (AET) uses a digital PIN diode electronic tuner, an adjustable directional coupler, two circulators and a power amplifier to create a compact load pull tuner device able of generating octave frequency band virtual reflection factors |Gamma|1 at milli-second tuning speed.

A drive circuit for a power semiconductor element according to the present disclosure includes: a control command unit that outputs a turn-on command for a power semiconductor element; a gate voltage detection unit that detects a gate voltage applied to a gate terminal after the control command unit outputs the turn-on command; a differentiator that subjects the gate voltage detected by the gate voltage detection unit to time differentiation; and a determination unit that determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not.

A semiconductor test equipment can conduct a burn-in test, and has a testing table capable of aligning a plurality of contact units formed of a probe card having a plurality of contact probes each corresponding to each of a plurality of semiconductor chips formed on a semiconductor wafer to contact with the semiconductor wafer, and a holding tool for holding the semiconductor wafer and the probe card in a contacted state; a voltage application circuit having connection wiring lines provided in a manner capable of parallel connection of the plurality of contact units aligned on the testing table, and a plurality of connection units to apply a testing voltage to the semiconductor wafer held on each of the plurality of contact units; and a characteristic measuring circuit for measuring characteristics of the plurality of semiconductor chips formed on the semiconductor wafer according to application of the testing voltage.

A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), I.sub.OFF represents the off-state current, t represents time during which the transistor is off, and are constants, is a constant that satisfies 0<1, and C.sub.S is a constant that represents load capacitance of a source or a drain.

[00001]$\begin{array}{cc}{I}_{\mathrm{OFF}}\left(t\right)=C_S\frac{}{{}^{}}{t}^{-1}{e}^{-{\left(\frac{t}{}\right)}^{}}& \left(\mathrm{a2}\right)\end{array}$

A power transistor, a driver and an output stage. The power transistor includes an active region and a metallization level located above the active region for power distribution and for detecting an imminent metallization error induced by stress (RPP stress) caused by repeated power pulses. The power transistor also includes a further metallization level, which is located above the metallization level and in which galvanically isolated metal elements extend mutually parallel in a direction of extent, of which one pair is used for energizing the power transistor. It is a characteristic of the power transistor that at least one cut-out is formed above the active region in the further metallization level. The cut-out has the effect of decreasing heat dissipation. The power transistor is thereby heated more intensely in the localized region, so that large temperature gradients occur in the transition region defined by the edges of the metal elements.

A device analysis apparatus is a device analysis apparatus for determining a quality of a power semiconductor device, including an application unit that applies a voltage signal to the power semiconductor device, a light detection unit that detects light from the power semiconductor device at a plurality of detection positions and outputs detection signals based on detection results, and a determination unit that determines the quality of the power semiconductor device based on temporal changes of the detection signals.

A system for determining an amount of time skew between two measurement probes includes a first probe and a second probe and one or more processors configured to measure a current signal from a Device Under Test (DUT) through the first probe, measure a voltage signal from the DUT through the second probe, generate a modeled voltage signal from the measured current signal, compare the modeled voltage signal to the measured voltage signal, and determine the amount of time skew between the first and the second probe from the compared signals. Methods are also described.

A method is for testing the functionality of a switching member including at least one switching element. A switching state is influenced via a control input of the switching element and via a control signal generated and output to the control input. An activation signal is output to the control unit and changes the control signal. The activation signal induces a test signal as the change to the control signal and induces a disconnection pulse as the test signal. The SiC or GaN power semiconductor is switched off via the disconnection pulse and conducts current in the reverse direction. In response to the disconnection pulse, the voltage drop is recorded. A comparison is carried out between an indicator and a reference encoding an expected response to the disconnection pulse. Depending on the result of the comparison, a status signal is generated which encodes the functionality of the switching member.

An inspection device comprises a stage for placing a device under test thereon, a dynamic characteristics test probe, a static characteristics test probe, and a control device configured to perform positional control by moving at least one of the stage, the dynamic characteristics test probe, and the static characteristics test probe. The control device performs the positional control such that the dynamic characteristics test probe is set to a dynamic characteristics test state in which the dynamic characteristics test probe is brought into contact with the electrode when the dynamic characteristics test is performed, and performs the positional control such that the static characteristics test probe is set to a static characteristics test state in which the static characteristics test probe is brought into contact with the electrode while the dynamic characteristics test probe is separated from the electrode when the static characteristics test is performed.

A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), I.sub.OFF represents the off-state current, t represents time during which the transistor is off, and are constants, is a constant that satisfies 0<1, and C.sub.S is a constant that represents load capacitance of a source or a drain. $\begin{array}{cc}{I}_{\mathrm{OFF}}\left(t\right)=C_S\frac{}{{}^{}}{t}^{-1}{e}^{-{\left(\frac{t}{}\right)}^{}}& \left(a2\right)\end{array}$