A system for monitoring a circuit, comprising a device under test, such as a power field effect transistor or capacitor, coupled to a power source and a signal source and configured to generate a power output using the signal source, a current output, a voltage output and an end of life detector coupled to the current output and the voltage output and configured to generate a first impedance as a function of the current output and the voltage output, to compare the first impedance to a second impedance and to generate an indicator if the first impedance exceeds the second impedance.

A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

A state estimation system for a power conversion semiconductor apparatus in an embodiment includes an analysis processing unit and an estimation processing unit. The analysis processing unit projects points indicating a combination of a voltage detection value in first time history data of a voltage between the pair of main terminals detected when the pair of main terminals are forward-biased and when the pair of main terminals are reverse-biased and a current detection value in second time history data of detection values of both a forward current and a reverse current between the pair of main terminals onto a coordinate plane including a voltage axis and a current axis on the basis of the first time history data and the second time history data in the power conversion semiconductor apparatus including the pair of main terminals and derives a distribution of the projected points on the coordinate plane. An estimation processing unit estimates a state of the power conversion semiconductor apparatus on the basis of a distribution of the projected points.

A method for detecting defects in a GaN high electron mobility transistor is disclosed. The method includes steps of measuring a plurality of electrical characteristics of a GaN high electron mobility transistor, measuring the plurality of electrical characteristics after performing a deterioration test on the GaN high electron mobility transistor, irradiating the GaN high electron mobility transistor in turns with a plurality of light sources with different wavelengths and measuring the plurality of electrical characteristics after each irradiation of the GaN high electron mobility transistor by each of the plurality of light sources, and comparing changes of the plurality of electrical characteristics measured in the above steps to determine the defect location of the GaN high electron mobility transistor.

A system for testing a subject transistor with constant power. The system may include an amplifier, a measurement voltage source, and a exercise voltage source. The amplifier may have an output connected to a gate of the subject transistor. The amplifier may have a first input and a second input. The measurement voltage source may be connected to the first input of the amplifier for use in measuring characteristics of the subject transistor. The exercise voltage source may be connected to the first input of the amplifier for exercising the subject transistor. The second input of the amplifier may be connected to a source of the subject transistor through a resistor.

Systems, methods, computer-readable media, techniques, and methodologies are disclosed for performing fault detection and prediction for power electronics and switching devices for power electronics. Systems and methods can determine, using a machine learning model, a prediction for a value of a first switching parameter of a switching device, the prediction based on the present value of a second switching parameter of a switching device and a prior value of the first switching parameter. Systems and methods disclosed herein can further determine a residual comprising the difference between the prediction and an actual value of the switching parameter, generate a test statistic based on the residual, and compare the test statistic to a first threshold value. Systems and methods disclosed herein can determine the presence of a fault in the switching device based on a comparison of the test statistic to a threshold value.

An optically-monitored and/or optically-controlled electronic device is described. The device includes at least one of a semiconductor transistor or a semiconductor diode. An optical detector is configured to detect light emitted by the at least one of the semiconductor transistor or the semiconductor diode during operation. A signal processor is configured to communicate with the optical detector to receive information regarding the light detected. The signal processor is further configured to provide information concerning at least one of an electrical current flowing in, a temperature of, or a condition of the at least one of the semiconductor transistor or the semiconductor diode during operation.

Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.

A gate resistance adjustment device has a waveform input unit that inputs waveforms of a drain voltage or a collector voltage and a drain current or a collector current at least one of during which a switching device is turned on and during which the switching device is turned off, an extraction unit that extracts time required for at least one of turning on or off the switching device and a steady-state drain current or a steady-state collector current of the switching device based on the waveforms input by the waveform input unit, a calculator that calculates a gate resistance of the switching device based on the time and the steady-state drain current or the steady-state collector current that are extracted by the extraction unit, and a setting unit that sets a gate resistance calculated by the calculator in the switching device.