Provided is a method of determining a gate capacitance of a semiconductor device having a source, a drain, a gate, and a channel, the semiconductor device being arranged in a circuit further comprising an electrical resonator, wherein one of the source, the drain, and the gate is connected to the electrical resonator. The method comprises: measuring a resonance frequency of the circuit; and calculating, based on the resonance frequency, the gate capacitance. Since it is not necessary to pass a current through the semiconductor device, an accurate measurement of gate capacitance may be achieved. Also provided are an apparatus for determining a gate capacitance, a probe for measuring gate capacitance, and a related computer program product.

An optically-monitored and/or optically-controlled electronic device is described. The device includes at least one of a semiconductor transistor or a semiconductor diode. An optical detector is configured to detect light emitted by the at least one of the semiconductor transistor or the semiconductor diode during operation. A signal processor is configured to communicate with the optical detector to receive information regarding the light detected. The signal processor is further configured to provide information concerning at least one of an electrical current flowing in, a temperature of, or a condition of the at least one of the semiconductor transistor or the semiconductor diode during operation.

Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.

Hardware test systems are provided that have an electrical test loop with a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500 A/μs and a minimum parasitic inductance of less than 100 nH. The hardware tests systems can be used for commutation measurement or other test applications requiring low stray inductance.

A method for manufacturing a semiconductor device includes preparing a wafer that includes semiconductor elements, placing the wafer on a stage so that a second electrode is in contact with a place surface of the stage, and measuring an on-resistance of at least one of the semiconductor elements with a first measurement terminal and a second measurement terminal. The on-resistance is measured by contacting the first measurement terminal to a first electrode of one of the semiconductor elements to be measured while applying a control signal to a control electrode of the one of the semiconductor elements, contacting the second measurement terminal to a first electrode of another one of the semiconductor elements while applying the control signal to a control electrode of the another one of the semiconductor elements, and measuring a resistance between the first measurement terminal and the second measurement terminal.

According to one embodiment, a current detecting circuit includes: a normally-ON type first switching element that includes a drain, a source, and a gate; a normally-OFF type second switching element including a drain that is connected to the source of the first switching element, a source that is connected to the gate of the first switching element, and a gate; and a differential amplification circuit that outputs a voltage according to a voltage between the drain and the source of the second switching element.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

A method of monitoring the health of a semiconductor power electronic switch such as an insulated gate bipolar transistor (IGBT) is provided. The method having the steps of: measuring one or more parameters selected from the group consisting of: a rate of change of voltage

[00001]$\left(\frac{\mathrm{dV}}{\mathrm{dt}}\right)$

across the switch; a rate of change of current

[00002]$\left(\frac{\mathrm{di}}{\mathrm{dt}}\right)$

through the switch, a charge present on a gate of the switch (Q.sub.G), a peak overshoot voltage (V.sub.PO) across the switch, and a peak overshoot or reverse recovery current (I.sub.RR) through the switch; and estimating the health of the switch based on the measured parameter(s).

Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.