A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality of HKMG fin field effect transistors are located, and the analysis method comprises: performing acceptance testing on the wafer to be tested; constructing an N-type model based on the position of each N-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, constructing a P-type model based on the position of each P-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, and constructing an N/P ratio model corresponding to the surface of the wafer to be tested based on the N-type model and the P-type model; and identifying the N/P ratio model based on a preset standard wafer model to determine whether the wafer to be tested is compliant based on the N/P ratio model. According to the analysis method provided by the present disclosure, it is possible to find a non-compliant wafer among a plurality of wafers, thereby enabling the subsequent targeted parameter analysis and improving the efficiency of optimizing the process scheme.

A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.

A device for monitoring at least three battery cells connected in series. The device includes, for each battery cell, a measuring circuit associated with the battery cell, which measuring circuit has an electrical load and can be switched by a controllable switching element such that the electrical load can be connected into a path parallel to the battery cell associated with the measuring circuit. A control unit that is designed to switch a first measuring circuit, which is associated with the first battery cell, and a third measuring circuit, which is associated with the third battery cell, such that the electrical loads of the two measuring circuits are each connected into the path parallel to the battery cell associated with the respective measuring circuit, and to ascertain whether the switching element of the first measuring circuit is switching correctly.

To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including:

acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and

assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

According to one embodiment, a current detecting circuit includes: a normally-ON type first switching element that includes a drain, a source, and a gate; a normally-OFF type second switching element including a drain that is connected to the source of the first switching element, a source that is connected to the gate of the first switching element, and a gate; and a differential amplification circuit that outputs a voltage according to a voltage between the drain and the source of the second switching element.

In a power supply system, a high-side (HS) insulated-gate bipolar transistor (IGBT) has a first collector, a first gate, and a first emitter. A low-side (LS) IGBT has a second collector coupled to the first emitter, a second gate, and a second emitter. A gate drive circuit is coupled to the first gate of the HS IGBT and the second gate of the LS IGBT. A control circuit is coupled to the gate drive circuit. The control circuit is configured to control the gate drive circuit for biasing the HS IGBT to a HS saturation, and determine a HS degradation of the HS IGBT based on a HS digitized gate voltage of the HS IGBT in the HS saturation.

An electrical device having a clocked circuitry, and a method for testing the power supply unit of the electrical device. The electrical device comprises an electrical load, a clocked power supply unit, at least one pulse transformer and an evaluation device. The power supply unit comprises a power stack having at least one power semiconductor switch and is configured for generating a clocked voltage for the electrical load from an electric voltage based on an alternating on/off switching of the power semiconductor switch. The power stack exhibits at least one current path, through which an electric current flows during operation. The pulse transformer generates a signal assigned to the change in the charge and/or the direction of the electric current flowing through the current path. The evaluation device evaluates the signal coming from the pulse transformer and draws a conclusion regarding the operational reliability of the power semiconductor switch.

A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.