A universal switching platform is configured to test a device under test, and includes a first power source, a first switch, a second switch and a second power source. The first switch, the second switch and the second power source are coupled in series between positive and negative terminals of the first power source. The common node of the first and second switches and the negative terminal of the first power source are configured to be respectively coupled to first and second terminals of the device under test. The universal switching platform provides a voltage and a current to test the device under test when the first and second switches are controlled to transition between conduction and non-conduction.

A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

A dummy element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a first resistive layer deposited on the lower insulating film; an interlayer insulating film covering the first resistive layer; a first pad-forming electrode deposited on the interlayer insulating film so as to be connected to the first resistive layer, and including an extending portion to be in Schottky contact with the semiconductor substrate; a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact; and a counter electrode allocated under the semiconductor substrate, the dummy element simulating a defective state in the lower insulating film and the interlayer insulating film immediately under the first pad-forming electrode included in a corresponding resistive element as a target to be examined.

A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure. Methodology entails measuring a capacitance between the detection structure and the substrate, measuring another capacitance between the reference structure and substrate, and comparing the two capacitances to determine whether defects exist.

A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.

A semi-insulating compound semiconductor substrate includes a semi-insulating compound semiconductor, the semi-insulating compound semiconductor substrate being configured such that, on a major plane having a plane orientation of (100), a standard deviation/average value of specific resistance measured at intervals of 0.1 mm along equivalent four directions in a <110> direction from a center of the major plane, and a standard deviation/average value of specific resistance measured at intervals of 0.1 mm along equivalent four directions in a <100> direction from the center of the major plane are each not more than 0.1.

According to an embodiment of the present invention, a system for non-invasively characterizing a qubit device includes a characterization probe chip. The characterization probe chip includes a substrate and a characterization resonator formed on a first surface of the substrate. The characterization resonator includes a superconducting stripline, and a superconducting antenna coupled to an end of the superconducting stripline, the superconducting antenna positioned to align with a qubit on the qubit device being characterized. The characterization probe chip also includes and a superconducting ground plane formed on a second surface of the substrate, the second surface opposing the first surface. In operation, the superconducting antenna is configured to capacitively couple the characterization resonator to the qubit aligned with the superconducting antenna for characterization of the qubit.

According to an embodiment of the present invention, a system for non-invasively characterizing a qubit device includes a characterization probe chip. The characterization probe chip includes a substrate and a characterization resonator formed on a first surface of the substrate. The characterization resonator includes a superconducting stripline, and a superconducting antenna coupled to an end of the superconducting stripline, the superconducting antenna positioned to align with a qubit on the qubit device being characterized. The characterization probe chip also includes and a superconducting ground plane formed on a second surface of the substrate, the second surface opposing the first surface. In operation, the superconducting antenna is configured to capacitively couple the characterization resonator to the qubit aligned with the superconducting antenna for characterization of the qubit.

We disclose herein a method for testing and/or calibrating a thermopile based device. The method comprising: applying an electrical bias of a first polarity to the thermopile based device and measuring a first value of an electrical parameter; and applying an electrical bias of a second polarity to the thermopile based device and measuring a second value of an electrical parameter.

A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure. Methodology entails measuring a capacitance between the detection structure and the substrate, measuring another capacitance between the reference structure and substrate, and comparing the two capacitances to determine whether defects exist.