A method of diagnosing a load port includes identifying a plurality of entities for a plurality of substrate storage containers by a plurality of load ports capable of transferring a substrate into and out of the plurality of substrate storage containers; detecting directly or indirectly a plurality of states of the plurality of substrate storage containers by a plurality of sensors provided at the plurality of load ports; associating the plurality of load ports, the plurality of entities and a plurality of sensor values, with each other; accumulating, in a database, data associated in the act of associating the plurality of load ports, the plurality of entities, and the plurality of sensor values; and analyzing the data in the database and determining a state of each of the plurality of load ports.

A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.

This inspection device inspects an imaging device formed in an object to be inspected by bringing a contact terminal into electrical contact with a wiring layer of the imaging device while causing light to enter the imaging device, wherein the light enters the imaging device from a back surface that is a surface on the side reverse to the side on which the wiring layer is provided, and the inspection device is provided with: a mounting table which is formed from a light transmissive material and on which the object to be inspected is mounted in such a manner that the mounting table faces the back surface of the imaging device; and a light irradiation mechanism which is disposed to face the object to be inspected with the mounting table interposed therebetween, and which has a plurality of LEDs oriented toward the object to be inspected.

The invention discloses a fabrication process variation analysis method of a silicon-based Mach-Zehnder electro-optic modulator. The method includes the following steps: (1) use the input reflection coefficient S.sub.11 to characterize and quantify the reflection deviation characteristics of the driving signal on the traveling wave electrode; (2) measure and quantify the modulated signal characteristics of the silicon Mach-Zehnder electro-optic modulator. The modulated signal characteristics include transmission characteristics, vertical direction characteristics and horizontal direction characteristics; (3) Pearson correlation coefficient and partial correlation coefficient are introduced. By analyzing the value and variation trend of Pearson correlation coefficient and partial correlation coefficient, the relationship between the deviation of the driving signal reflection and the deviation of the modulated signal characteristics is analyzed. The method of the present invention can establish the relationship between fabrication process control and performance analysis at the device level, and help to develop device designs with better fabrication tolerances.

An online monitoring system for measuring the on-state voltage drop of power semiconductor devices comprises a voltage withstanding circuit and a voltage clamping circuit, one terminal of the voltage withstanding circuit is connected to one terminal of the voltage clamping circuit, and the other terminals of the voltage withstanding circuit and the voltage clamping circuit are randomly connected to two terminals of the power semiconductor device under test (DUT) respectively. The two terminals of the voltage clamping circuit are output terminals of the online monitoring system. A clamping voltage of the voltage clamping circuit is higher than the on-state voltage drop of the DUT. When the DUT is off, the output voltage of the system is fixed to the clamping voltage, and when it is on, the output voltage is not clamped. The system has simplified structure and enables convenient, accurate and low-cost measurement of on-state voltage drop.

A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.

An apparatus for estimating the lifetime of a surge protective device (SPD) using the discharge characteristics of a metal oxide varistor (MOV) includes an MOV having an input terminal and an output terminal; an impulse voltage application unit applying an impulse voltage for MOV test to the input terminal of the MOV; a discharge current measurement unit; a first switching unit connecting a power line to the input terminal of the MOV; a second switching unit connecting a ground line to the output terminal of the MOV in the normal mode and selectively connecting the discharge current measurement unit in the MOV test mode; an MOV test management unit providing information; a discharge current check unit generating an MOV abnormal signal; and an MOV state display unit displaying an MOV abnormal signal.

A testing apparatus includes a holster including a jack defining a conductive periphery configured to connect with a reference lead of the voltage probe to form a common ground. The apparatus includes a shunt defining first and second regions of different potential having predetermined difference. The second region is configured to connect with a reference lead of the shunt probe. The apparatus includes a bridge configured to connect the shunt probe lead with the common ground.

A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure. Methodology entails measuring a capacitance between the detection structure and the substrate, measuring another capacitance between the reference structure and substrate, and comparing the two capacitances to determine whether defects exist.

An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.