A testing circuit includes at least one sub-circuit. The sub-circuit includes a first input end, at least one second input end, at least one third input end, and at least one driving output end. The first switch unit includes controllable switches. The second switch unit includes sub-units and first inverters. The sub-unit includes transmission gates. The control end of the controllable switch connects to the second input end, the first end connects to the first input end, and the second end connects to the input end of the transmission gate. The first control end of the transmission gate connects to the third input end and the input end of the first inverter, the second control end connects to the output end of the first inverter, the output end connects to the driving output end.

A bonding quality test circuit includes a switching circuit configured to provide a connection between a sensing node and a bonding node, the bonding node corresponding to a first end of a bonding resistor that is between a line provided to a memory device and a peripheral circuit, a precharging circuit configured to provide a precharge voltage to the line and the sensing node when the precharging circuit is connected to the line and the sensing node by the switching circuit, a latch circuit that includes a first node configured to provide a control output signal to the precharging circuit and a second node configured to have a voltage that is phase inverted with respect to a voltage of the control output signal, and a first transistor configured to provide an output signal according to the sensing node when the first transistor is connected to the second node.

A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

A testing apparatus includes a holster including a jack defining a conductive periphery configured to connect with a reference lead of the voltage probe to form a common ground. The apparatus includes a shunt defining first and second regions of different potential having predetermined difference. The second region is configured to connect with a reference lead of the shunt probe. The apparatus includes a bridge configured to connect the shunt probe lead with the common ground.

An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.

A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using in situ, or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.

A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.

A method for detecting a fault in a thermoelectric device (102), the method comprising: applying a voltage across the thermoelectric device (102); ceasing to apply the voltage to the thermoelectric device (102) after a predefined period of time; measuring a Seebeck voltage V.sub.s across the thermoelectric device (102); comparing V.sub.s to a first threshold voltage V.sub.T; and creating a record of a fault if V.sub.s is below V.sub.T.