An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.

A testing circuit includes at least one sub-circuit. The sub-circuit includes a first input end, at least one second input end, at least one third input end, and at least one driving output end. The first switch unit includes controllable switches. The second switch unit includes sub-units and first inverters. The sub-unit includes transmission gates. The control end of the controllable switch connects to the second input end, the first end connects to the first input end, and the second end connects to the input end of the transmission gate. The first control end of the transmission gate connects to the third input end and the input end of the first inverter, the second control end connects to the output end of the first inverter, the output end connects to the driving output end.

Semiconductor module testing equipment includes a test board, a plurality of pipe structures extending from an upper surface of the test board in a first direction and spaced apart from one another in a second direction that intersects the first direction, wherein the first and second directions are substantially parallel to a plane of the test board, at least one semiconductor module socket disposed between a pair of neighboring pipe structures of the plurality of pipe structures, and a plurality of nozzles disposed on each pipe structure of the plurality of pipe structures, wherein the plurality of nozzles is configured to discharge a fluid laterally.

A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire1, a second interconnect parasitic resistor Rwire2, an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire1 and one end of the encapsulation network resistor Rnet. The other end of the Rwire1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire2. A positive electrode of the Dio_die is connected to the other end of the Rnet.

The apparatus for monitoring a photovoltaic system includes an incoupling circuit configured to couple an AC voltage test signal into the photovoltaic system, and an outcoupling circuit configured to outcouple a response signal, which is associated with the test signal, from the photovoltaic system, and an evaluation device, which is connected to the outcoupling circuit. The evaluation device is configured to identify events which adversely affect correct operation of the photovoltaic system. The apparatus is distinguished in that the outcoupling circuit includes a first transformer and a second transformer, each having a respective primary winding and each having a respective secondary winding which is connected to the evaluation device, with the primary windings of the first and second transformers being arranged in different electrical lines between a generator and an inverter in the photovoltaic system. The disclosure also relates to a corresponding method for monitoring a photovoltaic system.

Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

A probe device includes a measurement stage and an output connection. The measurement stage has a circuit configured to be connected with a power device under measurement, to measure one or more of a voltage or a current of the power device under measurement. The measurement stage is configured for at least one of a power supply rail or a reference of the measurement stage to be coupled to an electrode of the power device when the one or more of the voltage or the current is measured. The output connection is configured to communicate one or more of the voltage or the current of the power device under measurement that is measured or a derived parameter to a digital processing device or an external computer acquisition system.

A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.

An electronic circuit includes a first die, having a GaN transistor, and a second die, stacked so that an element of the second die electrically connects a first node and a second nodes of the first die respectively coupled to a conduction node and to a control node of the GaN transistor.

In one example, a method includes determining that an insulated-gate bipolar transistor (IGBT) is saturated, and while the IGBT is saturated, determining a collector-emitter saturation voltage (V.sub.CE.sub.Sat) of the IGBT.