There are provided systems and methods comprising obtaining design data of each of a plurality of given overlay targets comprising a plurality of stacked layers, using at least part of the design data to simulate image data of each given overlay target that would have been acquired by an electron beam examination system, using the image data to determine, before actual manufacturing of each given overlay target, second data informative of estimated probability that each given overlay target, upon being manufactured according to the design data, provides measurement data in an overlay measurement process meeting a measurement quality criterion, and using the second data of each given overlay target to select at least one optimal overlay target among the plurality of different overlay targets, wherein the at least one optimal overlay target is usable to be actually manufactured on the semiconductor specimen.

An electron beam absorbed current measurement method includes connecting a conductive probe to a conductive structure of a sample, irradiating a pulsed electron beam along the conductive structure to generate an alternating current in the conductive probe, and determining a presence of a high resistance defect in the conductive structure based on at least one of a delay of a rising edge of the alternating current waveform and a decrease in amplitude of the alternating current waveform.

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

A testing apparatus for a wafer having a plurality of semiconductor chips, each including one or more vias, includes an electron beam discharging unit, a detecting unit, and a controller. The electron beam discharging unit is configured to discharge an electron beam to a via of one of the semiconductor chips. The detecting unit generates a detection signal corresponding to a current flowing through the via. The controller is configured to record a value of the detection signal in association with a position of the semiconductor chip.

A method for making thin film transistor includes: providing a gate electrode and forming an insulating layer on the gate electrode; providing a carbon nanotube film comprising a plurality of metallic carbon nanotubes and a plurality of semiconducting carbon nanotubes; laying the carbon nanotube film on a surface of the insulating layer, and placing the carbon nanotube film under a scanning electron microscope to take photo of the carbon nanotube film to distinguish the plurality of metallic carbon nanotubes and the plurality of semiconducting carbon nanotubes; removing the metallic carbon nanotubes, and forming a source electrode and a drain electrode on a surface of the semiconducting layer.

An axis conversion technique is provided for the milling of lamellae for TEM analysis that includes a sputter deposition to prevent warpage of the axis-converted lamellae.

A method for making thin film transistor includes: providing a gate electrode and forming an insulating layer on the gate electrode; providing a carbon nanotube film comprising a plurality of metallic carbon nanotubes and a plurality of semiconducting carbon nanotubes; laying the carbon nanotube film on a surface of the insulating layer, and placing the carbon nanotube film under a scanning electron microscope to take photo of the carbon nanotube film to distinguish the plurality of metallic carbon nanotubes and the plurality of semiconducting carbon nanotubes; removing the metallic carbon nanotubes, and forming a source electrode and a drain electrode on a surface of the semiconducting layer.

The present invention provides a detection method for sensitive parts of ionization damage in a bipolar transistor, which includes the following steps: selecting an irradiation source, and carrying out irradiation test on the bipolar transistor to be tested; installing the irradiated bipolar transistor on a test bench of a deep level transient spectroscopy system, and setting test parameters; selecting at least two different bias voltages, and testing the bipolar transistor to obtain a deep level transient spectrum; determining whether a defect is an ionization defect according to a peak position of the defect signal in the deep level transient spectrum; determining the defect type as oxidation trapped charges or an interface state according to the level of the defect signal in the deep level transient spectrum; and determining the sensitive area of ionization damage in the bipolar transistor according to the determination result of the defect signal type.

A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.